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Conv TTL Blocking - Gateware
Commit 1253636a authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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added xil_multiboot to test_pulse project

parent 148ce7b6
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Showing with 210 additions and 130 deletions
hdl/release/syn/conv_ttl_blo.gise
View file @ 1253636a
...@@ -137,6 +137,8 @@ ...@@ -137,6 +137,8 @@
<transform xil_pn:end_ts="1382450282" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1382450228"> <transform xil_pn:end_ts="1382450282" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1382450228">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.pcf"/> <outfile xil_pn:name="conv_ttl_blo.pcf"/>
<outfile xil_pn:name="conv_ttl_blo_map.map"/> <outfile xil_pn:name="conv_ttl_blo_map.map"/>
......
hdl/test_pulse/syn/Makefile
View file @ 1253636a
...@@ -49,6 +49,10 @@ FILES := ../top/conv_ttl_blo.ucf \ ...@@ -49,6 +49,10 @@ FILES := ../top/conv_ttl_blo.ucf \
../../vbcp_wb/rtl/vbcp_wb.vhd \ ../../vbcp_wb/rtl/vbcp_wb.vhd \
../../glitch_filt/rtl/glitch_filt.vhd \ ../../glitch_filt/rtl/glitch_filt.vhd \
../../pulse_gen_gp/rtl/pulse_gen_gp.vhd \ ../../pulse_gen_gp/rtl/pulse_gen_gp.vhd \
../../multiboot/rtl/multiboot_regs.vhd \
../../multiboot/rtl/multiboot_fsm.vhd \
../../multiboot/rtl/spi_master.vhd \
../../multiboot/rtl/xil_multiboot.vhd \
../../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \ ../../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \ ../../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \ ../../../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
......
hdl/test_pulse/syn/conv_ttl_blo.gise
View file @ 1253636a
...@@ -30,6 +30,7 @@ ...@@ -30,6 +30,7 @@
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/> <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/> <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo.bgn" xil_pn:subbranch="FPGAConfiguration"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_BIN" xil_pn:name="conv_ttl_blo.bin"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="conv_ttl_blo.bit" xil_pn:subbranch="FPGAConfiguration"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="conv_ttl_blo.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="conv_ttl_blo.bld"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="conv_ttl_blo.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="conv_ttl_blo.cmd_log"/> <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="conv_ttl_blo.cmd_log"/>
...@@ -52,6 +53,7 @@ ...@@ -52,6 +53,7 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo.ut" xil_pn:subbranch="FPGAConfiguration"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="conv_ttl_blo.xpi"/> <file xil_pn:fileType="FILE_XPI" xil_pn:name="conv_ttl_blo.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="conv_ttl_blo.xst"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="conv_ttl_blo.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="conv_ttl_blo_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="conv_ttl_blo_guide.ncd" xil_pn:origination="imported"/> <file xil_pn:fileType="FILE_NCD" xil_pn:name="conv_ttl_blo_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_map.map" xil_pn:subbranch="Map"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_map.mrp" xil_pn:subbranch="Map"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_map.mrp" xil_pn:subbranch="Map"/>
...@@ -62,6 +64,7 @@ ...@@ -62,6 +64,7 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="conv_ttl_blo_pad.csv" xil_pn:subbranch="Par"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="conv_ttl_blo_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="conv_ttl_blo_pad.txt" xil_pn:subbranch="Par"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="conv_ttl_blo_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_par.xrpt"/> <file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="conv_ttl_blo_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="conv_ttl_blo_summary.xml"/> <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="conv_ttl_blo_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="conv_ttl_blo_usage.xml"/> <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="conv_ttl_blo_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_xst.xrpt"/> <file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_xst.xrpt"/>
...@@ -100,7 +103,7 @@ ...@@ -100,7 +103,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1379409237" xil_pn:in_ck="946591740309691062" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1379409214"> <transform xil_pn:end_ts="1382452837" xil_pn:in_ck="6118850150238794815" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1382452812">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -122,7 +125,7 @@ ...@@ -122,7 +125,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1379409247" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1379409237"> <transform xil_pn:end_ts="1382452844" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1382452837">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
...@@ -131,7 +134,7 @@ ...@@ -131,7 +134,7 @@
<outfile xil_pn:name="conv_ttl_blo.ngd"/> <outfile xil_pn:name="conv_ttl_blo.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/> <outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1379409344" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1379409247"> <transform xil_pn:end_ts="1382452953" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1382452844">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
...@@ -144,8 +147,9 @@ ...@@ -144,8 +147,9 @@
<outfile xil_pn:name="conv_ttl_blo_summary.xml"/> <outfile xil_pn:name="conv_ttl_blo_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_usage.xml"/> <outfile xil_pn:name="conv_ttl_blo_usage.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1379409414" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1379409344"> <transform xil_pn:end_ts="1382453024" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1382452953">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.ncd"/> <outfile xil_pn:name="conv_ttl_blo.ncd"/>
...@@ -158,18 +162,20 @@ ...@@ -158,18 +162,20 @@
<outfile xil_pn:name="conv_ttl_blo_pad.txt"/> <outfile xil_pn:name="conv_ttl_blo_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_par.xrpt"/> <outfile xil_pn:name="conv_ttl_blo_par.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1379409454" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1379409414"> <transform xil_pn:end_ts="1382453347" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3952527596078283548" xil_pn:start_ts="1382453308">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.bgn"/> <outfile xil_pn:name="conv_ttl_blo.bgn"/>
<outfile xil_pn:name="conv_ttl_blo.bin"/>
<outfile xil_pn:name="conv_ttl_blo.bit"/> <outfile xil_pn:name="conv_ttl_blo.bit"/>
<outfile xil_pn:name="conv_ttl_blo.drc"/> <outfile xil_pn:name="conv_ttl_blo.drc"/>
<outfile xil_pn:name="conv_ttl_blo.ut"/> <outfile xil_pn:name="conv_ttl_blo.ut"/>
<outfile xil_pn:name="webtalk.log"/> <outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1379409414" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1379409401"> <transform xil_pn:end_ts="1382453024" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1382453013">
<status xil_pn:value="FailedRun"/> <status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/test_pulse/syn/conv_ttl_blo.xise
View file @ 1253636a
...@@ -56,7 +56,7 @@ ...@@ -56,7 +56,7 @@
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/> <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
...@@ -146,6 +146,9 @@ ...@@ -146,6 +146,9 @@
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
...@@ -172,7 +175,7 @@ ...@@ -172,7 +175,7 @@
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/> <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/> <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="-g next_config_register_write:Disable" xil_pn:valueState="non-default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
...@@ -240,7 +243,7 @@ ...@@ -240,7 +243,7 @@
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
...@@ -302,6 +305,7 @@ ...@@ -302,6 +305,7 @@
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
...@@ -309,7 +313,7 @@ ...@@ -309,7 +313,7 @@
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
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...@@ -372,273 +376,285 @@ ...@@ -372,273 +376,285 @@
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<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="64"/> <association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="65"/> <association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="66"/> <association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="67"/> <association xil_pn:name="Implementation" xil_pn:seqID="67"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="68"/> <association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="69"/> <association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="70"/> <association xil_pn:name="Implementation" xil_pn:seqID="70"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="71"/> <association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/> <association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="73"/> <association xil_pn:name="Implementation" xil_pn:seqID="73"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="74"/> <association xil_pn:name="Implementation" xil_pn:seqID="74"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="75"/> <association xil_pn:name="Implementation" xil_pn:seqID="75"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="76"/> <association xil_pn:name="Implementation" xil_pn:seqID="76"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="77"/> <association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="78"/> <association xil_pn:name="Implementation" xil_pn:seqID="78"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="79"/> <association xil_pn:name="Implementation" xil_pn:seqID="79"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/> <association xil_pn:name="Implementation" xil_pn:seqID="80"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="81"/> <association xil_pn:name="Implementation" xil_pn:seqID="81"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="82"/> <association xil_pn:name="Implementation" xil_pn:seqID="82"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="83"/> <association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="84"/> <association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="85"/> <association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/> <association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/> <association xil_pn:name="Implementation" xil_pn:seqID="87"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="88"/> <association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="89"/> <association xil_pn:name="Implementation" xil_pn:seqID="89"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="90"/> <association xil_pn:name="Implementation" xil_pn:seqID="90"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="91"/> <association xil_pn:name="Implementation" xil_pn:seqID="91"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="92"/> <association xil_pn:name="Implementation" xil_pn:seqID="92"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="93"/> <association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="94"/> <association xil_pn:name="Implementation" xil_pn:seqID="94"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="95"/> <association xil_pn:name="Implementation" xil_pn:seqID="95"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="96"/> <association xil_pn:name="Implementation" xil_pn:seqID="96"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="97"/> <association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="98"/> <association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="99"/> <association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="100"/> <association xil_pn:name="Implementation" xil_pn:seqID="100"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="101"/> <association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="102"/> <association xil_pn:name="Implementation" xil_pn:seqID="102"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="105"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
</file>
</files> </files>
<bindings/> <bindings/>
......
hdl/test_pulse/top/Manifest.py
View file @ 1253636a
...@@ -9,6 +9,7 @@ modules = { ...@@ -9,6 +9,7 @@ modules = {
"../../bicolor_led_ctrl", "../../bicolor_led_ctrl",
"../../vbcp_wb", "../../vbcp_wb",
"../../pulse_gen_gp", "../../pulse_gen_gp",
"../../multiboot",
"../rtl" "../rtl"
], ],
"git" : [ "git" : [
......
hdl/test_pulse/top/conv_ttl_blo.ucf
View file @ 1253636a
...@@ -296,19 +296,18 @@ NET "fpga_ga_i[4]" IOSTANDARD = LVCMOS33; ...@@ -296,19 +296,18 @@ NET "fpga_ga_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_gap_i" LOC = H19; NET "fpga_gap_i" LOC = H19;
NET "fpga_gap_i" IOSTANDARD = LVCMOS33; NET "fpga_gap_i" IOSTANDARD = LVCMOS33;
###----------------------------------------------------------------------------- ##-----------------------------------------------------------------------------
###-- ROM memory ##-- ROM memory
###----------------------------------------------------------------------------- ##-----------------------------------------------------------------------------
#NET "fpga_prom_cclk_o" LOC = Y20; NET "fpga_prom_cclk_o" LOC = Y20;
#NET "fpga_prom_cclk_o" IOSTANDARD = "LVCMOS33"; NET "fpga_prom_cclk_o" IOSTANDARD = "LVCMOS33";
#NET "fpga_prom_cso_b_n_o" LOC = AA3; NET "fpga_prom_cso_b_n_o" LOC = AA3;
#NET "fpga_prom_cso_b_n_o" IOSTANDARD = "LVCMOS33"; NET "fpga_prom_cso_b_n_o" IOSTANDARD = "LVCMOS33";
#NET "fpga_prom_miso_i" LOC = AA20; NET "fpga_prom_miso_i" LOC = AA20;
#NET "fpga_prom_miso_i" IOSTANDARD = "LVCMOS33"; NET "fpga_prom_miso_i" IOSTANDARD = "LVCMOS33";
#NET "fpga_prom_mosi_o" LOC = AB20; NET "fpga_prom_mosi_o" LOC = AB20;
#NET "fpga_prom_mosi_o" IOSTANDARD = "LVCMOS33"; NET "fpga_prom_mosi_o" IOSTANDARD = "LVCMOS33";
#
#
###============================================================================= ###=============================================================================
###-- WHITE RABBIT ###-- WHITE RABBIT
###============================================================================= ###=============================================================================
......
hdl/test_pulse/top/conv_ttl_blo.vhd
View file @ 1253636a
...@@ -98,6 +98,12 @@ entity conv_ttl_blo is ...@@ -98,6 +98,12 @@ entity conv_ttl_blo is
fpga_ga_i : in std_logic_vector(4 downto 0); fpga_ga_i : in std_logic_vector(4 downto 0);
fpga_gap_i : in std_logic; fpga_gap_i : in std_logic;
-- Flash memory lines
fpga_prom_cclk_o : out std_logic;
fpga_prom_cso_b_n_o : out std_logic;
fpga_prom_mosi_o : out std_logic;
fpga_prom_miso_i : in std_logic;
-- It allows power sequencing of the 24V rail after a security delay -- It allows power sequencing of the 24V rail after a security delay
mr_n_o : out std_logic mr_n_o : out std_logic
); );
...@@ -123,40 +129,43 @@ architecture behav of conv_ttl_blo is ...@@ -123,40 +129,43 @@ architecture behav of conv_ttl_blo is
-- Number of Wishbone masters and slaves, for wb_crossbar -- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1; constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 3; constant c_nr_slaves : natural := 4;
----------------------------------------- -----------------------------------------
-- Memory map -- Memory map
-- * all registers are word-addressable -- * all registers are word-addressable
-- * all registers are word-aligned -- * all registers are word-aligned
----------------------------------------- -----------------------------------------
-- MEM [000-FFF] -- CONV_REGS [0x000-0x004]
-- PULSE_CNT [0x100-0x13F]
-- PGEN_CTRL [0x200-0x24F]
-- MULTIBOOT [0x300-0x31F]
----------------------------------------- -----------------------------------------
-- slave order definitions -- slave order definitions
constant c_slv_conv_regs : natural := 0; constant c_slv_conv_regs : natural := 0;
constant c_slv_pulse_cnt : natural := 1; constant c_slv_pulse_cnt : natural := 1;
constant c_slv_pgen_ctrl : natural := 2; constant c_slv_pgen_ctrl : natural := 2;
-- constant c_slv_mem : natural := 2; constant c_slv_multiboot : natural := 3;
-- base address definitions -- base address definitions
constant c_addr_conv_regs : t_wishbone_address := x"00000000"; constant c_addr_conv_regs : t_wishbone_address := x"00000000";
constant c_addr_pulse_cnt : t_wishbone_address := x"00000100"; constant c_addr_pulse_cnt : t_wishbone_address := x"00000100";
constant c_addr_pgen_ctrl : t_wishbone_address := x"00000200"; constant c_addr_pgen_ctrl : t_wishbone_address := x"00000200";
-- constant c_addr_mem : t_wishbone_address := x"00000100"; constant c_addr_multiboot : t_wishbone_address := x"00000300";
-- address mask definitions -- address mask definitions
constant c_mask_conv_regs : t_wishbone_address := x"00000F00"; constant c_mask_conv_regs : t_wishbone_address := x"00000F00";
constant c_mask_pulse_cnt : t_wishbone_address := x"00000F00"; constant c_mask_pulse_cnt : t_wishbone_address := x"00000F00";
constant c_mask_pgen_ctrl : t_wishbone_address := x"00000F00"; constant c_mask_pgen_ctrl : t_wishbone_address := x"00000F00";
-- constant c_mask_mem : t_wishbone_address := x"00000F00"; constant c_mask_multiboot : t_wishbone_address := x"00000F00";
-- addresses constant for Wishbone crossbar -- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0) constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= ( := (
c_slv_conv_regs => c_addr_conv_regs, c_slv_conv_regs => c_addr_conv_regs,
c_slv_pulse_cnt => c_addr_pulse_cnt, c_slv_pulse_cnt => c_addr_pulse_cnt,
c_slv_pgen_ctrl => c_addr_pgen_ctrl c_slv_pgen_ctrl => c_addr_pgen_ctrl,
-- c_slv_mem => c_addr_mem c_slv_multiboot => c_addr_multiboot
); );
-- masks constant for Wishbone crossbar -- masks constant for Wishbone crossbar
...@@ -164,8 +173,8 @@ architecture behav of conv_ttl_blo is ...@@ -164,8 +173,8 @@ architecture behav of conv_ttl_blo is
:= ( := (
c_slv_conv_regs => c_mask_conv_regs, c_slv_conv_regs => c_mask_conv_regs,
c_slv_pulse_cnt => c_mask_pulse_cnt, c_slv_pulse_cnt => c_mask_pulse_cnt,
c_slv_pgen_ctrl => c_mask_pgen_ctrl c_slv_pgen_ctrl => c_mask_pgen_ctrl,
--c_slv_mem => c_mask_mem c_slv_multiboot => c_addr_multiboot
); );
--============================================================================ --============================================================================
...@@ -206,8 +215,8 @@ architecture behav of conv_ttl_blo is ...@@ -206,8 +215,8 @@ architecture behav of conv_ttl_blo is
-- I2C address and status -- I2C address and status
i2c_addr_i : in std_logic_vector(6 downto 0); i2c_addr_i : in std_logic_vector(6 downto 0);
i2c_done_o : out std_logic; tip_o : out std_logic;
i2c_err_o : out std_logic; err_o : out std_logic;
-- Wishbone master signals -- Wishbone master signals
wbm_stb_o : out std_logic; wbm_stb_o : out std_logic;
...@@ -223,6 +232,27 @@ architecture behav of conv_ttl_blo is ...@@ -223,6 +232,27 @@ architecture behav of conv_ttl_blo is
); );
end component vbcp_wb; end component vbcp_wb;
-- Xilinx MultiBoot component
-- (use: remote reprogramming of the FPGA)
component xil_multiboot is
port
(
-- Clock and reset input ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone ports
wbs_i : in t_wishbone_slave_in;
wbs_o : out t_wishbone_slave_out;
-- SPI ports
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end component xil_multiboot;
-- Converter registers -- Converter registers
-- (use: ID, firmware version) -- (use: ID, firmware version)
component conv_regs is component conv_regs is
...@@ -391,8 +421,8 @@ architecture behav of conv_ttl_blo is ...@@ -391,8 +421,8 @@ architecture behav of conv_ttl_blo is
signal bicolor_led_state : std_logic_vector(23 downto 0); signal bicolor_led_state : std_logic_vector(23 downto 0);
-- VBCP bridge signals -- VBCP bridge signals
signal i2c_done : std_logic; signal vbcp_tip : std_logic;
signal i2c_err : std_logic; signal vbcp_err : std_logic;
signal i2c_err_led : std_logic; signal i2c_err_led : std_logic;
signal i2c_up : std_logic; signal i2c_up : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0); signal i2c_addr : std_logic_vector(6 downto 0);
...@@ -487,8 +517,8 @@ begin ...@@ -487,8 +517,8 @@ begin
-- I2C address and status -- I2C address and status
i2c_addr_i => i2c_addr, i2c_addr_i => i2c_addr,
i2c_done_o => i2c_done, tip_o => vbcp_tip,
i2c_err_o => i2c_err, err_o => vbcp_err,
-- Wishbone master signals -- Wishbone master signals
wbm_stb_o => xbar_slave_in(0).stb, wbm_stb_o => xbar_slave_in(0).stb,
...@@ -503,7 +533,7 @@ begin ...@@ -503,7 +533,7 @@ begin
wbm_err_i => xbar_slave_out(0).err wbm_err_i => xbar_slave_out(0).err
); );
-- Process to blink the LED for a finite amount of time when the i2c_done -- Process to blink the LED for a finite amount of time when the vbcp_tip
-- signal is set. -- signal is set.
p_i2c_blink : process(clk125) p_i2c_blink : process(clk125)
begin begin
...@@ -518,7 +548,7 @@ begin ...@@ -518,7 +548,7 @@ begin
when '0' => when '0' =>
led_i2c <= '0'; led_i2c <= '0';
if (i2c_done = '1') then if (vbcp_tip = '1') then
blink_state <= '1'; blink_state <= '1';
end if; end if;
...@@ -550,7 +580,7 @@ begin ...@@ -550,7 +580,7 @@ begin
if rising_edge(clk125) then if rising_edge(clk125) then
if (rst_n = '0') then if (rst_n = '0') then
i2c_err_led <= '0'; i2c_err_led <= '0';
elsif (i2c_err = '1') then elsif (vbcp_err = '1') then
i2c_err_led <= '1'; i2c_err_led <= '1';
end if; end if;
end if; end if;
...@@ -857,6 +887,28 @@ begin ...@@ -857,6 +887,28 @@ begin
--============================================================================ --============================================================================
inv_out_o <= inv_in_n_i; inv_out_o <= inv_in_n_i;
--============================================================================
-- MultiBoot logic
--============================================================================
xbar_master_in(c_slv_multiboot).int <= '0';
xbar_master_in(c_slv_multiboot).rty <= '0';
xbar_master_in(c_slv_multiboot).err <= '0';
cmp_multiboot : xil_multiboot
port map
(
clk_i => clk125,
rst_n_i => rst_n,
wbs_i => xbar_master_out(c_slv_multiboot),
wbs_o => xbar_master_in(c_slv_multiboot),
spi_cs_n_o => fpga_prom_cso_b_n_o,
spi_sclk_o => fpga_prom_cclk_o,
spi_mosi_o => fpga_prom_mosi_o,
spi_miso_i => fpga_prom_miso_i
);
--============================================================================ --============================================================================
-- Bicolor LED matrix logic -- Bicolor LED matrix logic
--============================================================================ --============================================================================
......
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