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Conv TTL Blocking - Gateware
Commit 148ce7b6 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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vbcp_wb corrections 

- corrected i2c_done_o high whenever a successful transfer occurs
in i2c_slave
- changed interface
(i2c_err_o is now err_o)
(i2c_done_o is now tip_o)
parent 1fa8d796
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Showing with 57 additions and 49 deletions
hdl/release/syn/conv_ttl_blo.gise
View file @ 148ce7b6
......@@ -103,7 +103,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1382359472" xil_pn:in_ck="3190287689474023470" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1382359451">
<transform xil_pn:end_ts="1382450222" xil_pn:in_ck="3190287689474023470" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1382450200">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -125,7 +125,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1382359479" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1382359472">
<transform xil_pn:end_ts="1382450228" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1382450222">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -134,11 +134,9 @@
<outfile xil_pn:name="conv_ttl_blo.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1382359619" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1382359479">
<transform xil_pn:end_ts="1382450282" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1382450228">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.pcf"/>
<outfile xil_pn:name="conv_ttl_blo_map.map"/>
......@@ -149,7 +147,7 @@
<outfile xil_pn:name="conv_ttl_blo_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1382359669" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1382359619">
<transform xil_pn:end_ts="1382450332" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1382450282">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -164,7 +162,7 @@
<outfile xil_pn:name="conv_ttl_blo_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1382431700" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3952527596078283548" xil_pn:start_ts="1382431666">
<transform xil_pn:end_ts="1382450366" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-3614567692198564809" xil_pn:start_ts="1382450332">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -177,7 +175,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1382359669" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1382359661">
<transform xil_pn:end_ts="1382450332" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1382450324">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/release/syn/conv_ttl_blo.xise
View file @ 148ce7b6
......@@ -175,7 +175,7 @@
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="-g next_config_register_write:Disable" xil_pn:valueState="non-default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -202,7 +202,7 @@
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
......
hdl/release/top/conv_ttl_blo.vhd
View file @ 148ce7b6
......@@ -125,7 +125,7 @@ architecture behav of conv_ttl_blo is
-- Constant declarations
--============================================================================
-- Firmware version
constant c_fwvers : std_logic_vector(15 downto 0) := x"0201";
constant c_fwvers : std_logic_vector(15 downto 0) := x"0200";
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
......@@ -240,10 +240,17 @@ architecture behav of conv_ttl_blo is
scl_i : in std_logic;
scl_o : out std_logic;
-- I2C address and status
-- I2C address
i2c_addr_i : in std_logic_vector(6 downto 0);
i2c_done_o : out std_logic;
i2c_err_o : out std_logic;
-- Transfer In Progress (TIP) and Error outputs
-- TIP : '1' when the I2C slave detects a matching I2C address, thus a
-- transfer is in progress
-- '0' when idle
-- ERR : '1' when the SysMon attempts to access an invalid WB slave
-- '0' when idle
tip_o : out std_logic;
err_o : out std_logic;
-- Wishbone master signals
wbm_stb_o : out std_logic;
......@@ -383,8 +390,8 @@ architecture behav of conv_ttl_blo is
signal xbar_master_out : t_wishbone_master_out_array(c_nr_slaves - 1 downto 0);
-- I2C bridge signals
signal i2c_done : std_logic;
signal i2c_err : std_logic;
signal vbcp_tip : std_logic;
signal vbcp_err : std_logic;
signal i2c_err_led : std_logic;
signal i2c_up : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0);
......@@ -455,8 +462,10 @@ begin
-- I2C address and status
i2c_addr_i => i2c_addr,
i2c_done_o => i2c_done,
i2c_err_o => i2c_err,
-- TIP and ERR outputs
tip_o => vbcp_tip,
err_o => vbcp_err,
-- Wishbone master signals
wbm_stb_o => xbar_slave_in(0).stb,
......@@ -471,7 +480,7 @@ begin
wbm_err_i => xbar_slave_out(0).err
);
-- Process to blink the LED for a finite amount of time when the i2c_done
-- Process to blink the LED for a finite amount of time when the vbcp_tip
-- signal is set.
p_i2c_blink : process(clk125)
begin
......@@ -486,7 +495,7 @@ begin
when '0' =>
led_i2c <= '0';
if (i2c_done = '1') then
if (vbcp_tip = '1') then
blink_state <= '1';
end if;
......@@ -518,7 +527,7 @@ begin
if rising_edge(clk125) then
if (rst_n = '0') then
i2c_err_led <= '0';
elsif (i2c_err = '1') then
elsif (vbcp_err = '1') then
i2c_err_led <= '1';
end if;
end if;
......
hdl/vbcp_wb/rtl/vbcp_wb.vhd
View file @ 148ce7b6
......@@ -73,10 +73,17 @@ entity vbcp_wb is
scl_i : in std_logic;
scl_o : out std_logic;
-- I2C address and status
-- I2C address
i2c_addr_i : in std_logic_vector(6 downto 0);
i2c_done_o : out std_logic;
i2c_err_o : out std_logic;
-- Transfer In Progress (TIP) and Error outputs
-- TIP : '1' when the I2C slave detects a matching I2C address, thus a
-- transfer is in progress
-- '0' when idle
-- ERR : '1' when the SysMon attempts to access an invalid WB slave
-- '0' when idle
tip_o : out std_logic;
err_o : out std_logic;
-- Wishbone master signals
wbm_stb_o : out std_logic;
......@@ -119,7 +126,6 @@ architecture behav of vbcp_wb is
signal tx_byte : std_logic_vector(7 downto 0);
signal rx_byte : std_logic_vector(7 downto 0);
signal done : std_logic;
signal i2c_err : std_logic;
signal done_d0 : std_logic;
signal stat : std_logic_vector(1 downto 0);
......@@ -187,9 +193,6 @@ begin
stat_o => stat
);
-- assert done output signal
i2c_done_o <= done;
--============================================================================
-- I2C to Wishbone bridge FSM logic
--============================================================================
......@@ -210,8 +213,6 @@ begin
-- data signal; shifting is handled inside the FSM.
tx_byte <= wb_dat_in(7 downto 0);
-- Assign the I2C error output
i2c_err_o <= i2c_err;
-- Finally, the FSM logic
p_fsm: process (clk_i) is
......@@ -227,7 +228,8 @@ begin
wb_we <= '0';
start_op <= '0';
ack_n <= '0';
i2c_err <= '0';
tip_o <= '0';
err_o <= '0';
adr_byte_cnt <= (others => '0');
dat_byte_cnt <= (others => '0');
......@@ -243,10 +245,12 @@ begin
-- address, start_op will be '0' (write).
---------------------------------------------------------------------
when ST_IDLE =>
err_o <= '0';
tip_o <= '0';
ack_n <= '0';
if (done = '1') and (stat = c_i2cs_addr_good) then
tip_o <= '1';
state <= ST_WB_ADR;
i2c_err <= '0';
ack_n <= '0';
start_op <= op;
end if;
......@@ -286,11 +290,11 @@ begin
wb_stb <= '0';
state <= ST_OP;
elsif (wb_err = '1') then
i2c_err <= '1';
ack_n <= '1';
wb_cyc <= '0';
wb_stb <= '0';
state <= ST_IDLE;
err_o <= '1';
ack_n <= '1';
wb_cyc <= '0';
wb_stb <= '0';
state <= ST_IDLE;
end if;
---------------------------------------------------------------------
......@@ -319,8 +323,7 @@ begin
elsif (stat = c_i2cs_addr_good) and (op /= start_op) then
state <= ST_SYSMON_RD_WB;
else
i2c_err <= '1';
state <= ST_IDLE;
state <= ST_IDLE;
end if;
end if;
......@@ -341,8 +344,7 @@ begin
state <= ST_SYSMON_WR_WB;
end if;
else
--i2c_err <= '1';
state <= ST_IDLE;
state <= ST_IDLE;
end if;
end if;
......@@ -362,7 +364,7 @@ begin
wb_we <= '0';
state <= ST_SYSMON_WR; --ST_IDLE;
elsif (wb_err = '1') then
i2c_err <= '1';
err_o <= '1';
state <= ST_IDLE;
end if;
......@@ -383,10 +385,10 @@ begin
wb_stb <= '0';
state <= ST_SYSMON_RD;
elsif (wb_err = '1') then
i2c_err <= '1';
wb_cyc <= '0';
wb_stb <= '0';
state <= ST_IDLE;
err_o <= '1';
wb_cyc <= '0';
wb_stb <= '0';
state <= ST_IDLE;
end if;
---------------------------------------------------------------------
......@@ -403,8 +405,7 @@ begin
state <= ST_IDLE;
end if;
else
i2c_err <= '1';
state <= ST_IDLE;
state <= ST_IDLE;
end if;
end if;
......
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