Change register MSWR to OSWR

OSWR also now contains 32 bits, to allow for 32 switches in addition to the existing 8 general-purpose ones.

Change register MSWR to OSWR
OSWR also now contains 32 bits, to allow for 32 switches in addition to the existing 8 general-purpose ones.
d69919e6 · Theodor-Adrian Stana · 885b948c · d69919e6 · d69919e6 · d69919e6
Commit d69919e6 authored Sep 25, 2014 by Theodor-Adrian Stana
Showing with 10 additions and 38 deletions

conv_regs.vhd modules/conv_regs.vhd +2 -30

conv_regs.wb modules/conv_regs.wb +4 -4

conv_common_gw.vhd top/conv_common_gw.vhd +2 -2

conv_common_gw_pkg.vhd top/conv_common_gw_pkg.vhd +2 -2

No files found.
--- a/modules/conv_regs.vhd
+++ b/modules/conv_regs.vhd
@@ -171,7 +171,7 @@ entity conv_regs is
 -- Port for std_logic_vector field: 'Input failsafe state' in reg: 'LSR'
    reg_lsr_rearfs_i                         : in     std_logic_vector(5 downto 0);
 -- Port for std_logic_vector field: 'Multicast address (from switch)' in reg: 'MSWR'
-    reg_mswr_switches_i                      : in     std_logic_vector(3 downto 0)
+    reg_oswr_switches_i                      : in     std_logic_vector(31 downto 0)
  );
 end conv_regs;

@@ -815,35 +815,7 @@ begin
          when "100011" => 
            if (wb_we_i = '1') then
            end if;
-            rddata_reg(3 downto 0) <= reg_mswr_switches_i;
-            rddata_reg(4) <= 'X';
-            rddata_reg(5) <= 'X';
-            rddata_reg(6) <= 'X';
-            rddata_reg(7) <= 'X';
-            rddata_reg(8) <= 'X';
-            rddata_reg(9) <= 'X';
-            rddata_reg(10) <= 'X';
-            rddata_reg(11) <= 'X';
-            rddata_reg(12) <= 'X';
-            rddata_reg(13) <= 'X';
-            rddata_reg(14) <= 'X';
-            rddata_reg(15) <= 'X';
-            rddata_reg(16) <= 'X';
-            rddata_reg(17) <= 'X';
-            rddata_reg(18) <= 'X';
-            rddata_reg(19) <= 'X';
-            rddata_reg(20) <= 'X';
-            rddata_reg(21) <= 'X';
-            rddata_reg(22) <= 'X';
-            rddata_reg(23) <= 'X';
-            rddata_reg(24) <= 'X';
-            rddata_reg(25) <= 'X';
-            rddata_reg(26) <= 'X';
-            rddata_reg(27) <= 'X';
-            rddata_reg(28) <= 'X';
-            rddata_reg(29) <= 'X';
-            rddata_reg(30) <= 'X';
-            rddata_reg(31) <= 'X';
+            rddata_reg(31 downto 0) <= reg_oswr_switches_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>

--- a/modules/conv_regs.wb
+++ b/modules/conv_regs.wb
@@ -790,16 +790,16 @@ peripheral {
  };

  reg {
-    name = "MSWR";
-    description = "Multicast Switch Register";
+    name = "OSWR";
+    description = "Other Switch Register";
    prefix = "mswr";
    field {
-      name = "Multicast address (from switch)";
+      name = "Switch state";
      description = "1 -- switch is ON \
      0 -- switch is OFF";
      prefix = "switches";
      type = SLV;
-      size = 4;
+      size = 32;
      access_dev = WRITE_ONLY;
      access_bus = READ_ONLY;
    };

--- a/top/conv_common_gw.vhd
+++ b/top/conv_common_gw.vhd
@@ -168,7 +168,7 @@ entity conv_common_gw is

    -- Switch inputs (for readout from converter status register)
    sw_gp_i                 : in  std_logic_vector(7 downto 0);
-    sw_multicast_i          : in  std_logic_vector(3 downto 0);
+    sw_other_i              : in  std_logic_vector(31 downto 0);

    -- RTM lines
    rtmm_i                  : in  std_logic_vector(2 downto 0);
@@ -1170,7 +1170,7 @@ end generate gen_latest_timestamp_unused_chans;
      reg_lsr_rear_i           => line_rear,
      reg_lsr_rearfs_i         => line_rear_fs,

-      reg_mswr_switches_i      => sw_multicast_i
+      reg_oswr_switches_i      => sw_other_i
    );

  --============================================================================

--- a/top/conv_common_gw_pkg.vhd
+++ b/top/conv_common_gw_pkg.vhd
@@ -170,7 +170,7 @@ package conv_common_gw_pkg is

      -- Switch inputs (for readout from converter status register)
      sw_gp_i                 : in  std_logic_vector(7 downto 0);
-      sw_multicast_i          : in  std_logic_vector(3 downto 0);
+      sw_other_i              : in  std_logic_vector(31 downto 0);

      -- RTM lines
      rtmm_i                  : in  std_logic_vector(2 downto 0);
@@ -422,7 +422,7 @@ package conv_common_gw_pkg is
  -- Port for std_logic_vector field: 'Input failsafe state' in reg: 'LSR'
      reg_lsr_rearfs_i                         : in     std_logic_vector(5 downto 0);
  -- Port for std_logic_vector field: 'Multicast address (from switch)' in reg: 'MSWR'
-      reg_mswr_switches_i                      : in     std_logic_vector(3 downto 0)
+      reg_oswr_switches_i                      : in     std_logic_vector(31 downto 0)
    );
  end component conv_regs;