Changed LTSR load policy

The 125 MHz domain registers are loaded only once the 20 MHz clock domain registers are loaded. Like this, we avoid having different values in the registers in the two clock domains.

Changed LTSR load policy
The 125 MHz domain registers are loaded only once the 20 MHz clock domain registers are loaded. Like this, we avoid having different values in the registers in the two clock domains.
885b948c · Theodor-Adrian Stana · a7cd894b · 885b948c
Commit 885b948c authored Sep 24, 2014 by Theodor-Adrian Stana
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Showing with 19 additions and 36 deletions

conv_common_gw.vhd top/conv_common_gw.vhd +19 -36

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--- a/top/conv_common_gw.vhd
+++ b/top/conv_common_gw.vhd
@@ -349,6 +349,7 @@ architecture arch of conv_common_gw is
  -- Latest timestamp signals
  signal lts_ld_125           : std_logic_vector(c_max_nr_chans-1 downto 0);
+  signal lts_ld_rdy_125       : std_logic_vector(c_max_nr_chans-1 downto 0);
  signal lts_tai_125          : t_lts_tai;
  signal lts_cycles_125       : t_lts_cycles;
  signal lts_wrtag_125        : std_logic_vector(c_max_nr_chans-1 downto 0);
@@ -994,7 +995,8 @@ end generate;
          lts_cycles_125(i) <= (others => '0');
          lts_tai_125(i)    <= (others => '0');
          lts_wrtag_125(i)  <= '0';
-        elsif (lts_ld_125(i) = '1') then
+        -- load only when synchronized version in 20 MHz domain is ready
+        elsif (lts_ld_125(i) = '1') and (lts_ld_rdy_125(i) = '1') then
          lts_cycles_125(i) <= tm_cycles;
          lts_tai_125(i)    <= tm_tai;
          lts_wrtag_125(i)  <= buf_wrtag;
@@ -1004,42 +1006,22 @@ end generate;
  end process p_lts_125;
  -- Pulse synchronizer: sync. lts_ld from 125 MHz to 20MHz domain
-  p_sync_ld_125 : process(clk_125)
+gen_lts_ld_pulse_sync : for i in 0 to g_nr_chans-1 generate
-  begin
+  cmp_pulse_sync : gc_pulse_synchronizer2
-    if rising_edge(clk_125) then
+    port map
-      for i in 0 to g_nr_chans-1 loop
+    (
-        if (rst_125_n = '0') then
+      clk_in_i    => clk_125,
-          lts_ld_toggle(i) <= '0';
+      rst_in_n_i  => rst_125_n,
-        elsif (lts_ld_125(i) = '1') then
-          lts_ld_toggle(i) <= not lts_ld_toggle(i);
-        else
-          -- useless, but placed here for clarity of the circuit
-          lts_ld_toggle(i) <= lts_ld_toggle(i);
-        end if;
-      end loop;
-    end if;
-  end process p_sync_ld_125;
-  p_sync_ld_20 : process(clk_20_i)
+      clk_out_i   => clk_20_i,
-  begin
+      rst_out_n_i => rst_20_n,
-    if rising_edge(clk_20_i) then
-      for i in 0 to g_nr_chans-1 loop
+      d_ready_o   => lts_ld_rdy_125(i),
-        if (rst_20_n = '0') then
-          lts_ld_20(i)        <= '0';
+      d_p_i       => lts_ld_125(i),
-          lts_ld_toggle_d0(i) <= '0';
+      q_p_o       => lts_ld_20(i)
-          lts_ld_toggle_d1(i) <= '0';
+    );
-        else
+end generate gen_lts_ld_pulse_sync;
-          lts_ld_toggle_d0(i) <= lts_ld_toggle(i);
-          lts_ld_toggle_d1(i) <= lts_ld_toggle_d0(i);
-          -- avoid garbled data in regs by disabling load pulse on WB transfer
-          if (xbar_master_out(c_slv_conv_regs).stb = '0') and
-             (xbar_master_out(c_slv_conv_regs).cyc = '0') then
-            lts_ld_20(i) <= lts_ld_toggle_d0(i) xor lts_ld_toggle_d1(i);
-          end if;
-        end if;
-      end loop;
-    end if;
-  end process p_sync_ld_20;
  -- Latest timestamp regs in 20MHz clock domain
  p_lts_20 : process (clk_20_i)
@@ -1064,6 +1046,7 @@ end generate;
 gen_latest_timestamp_unused_chans : if (g_nr_chans < c_max_nr_chans) generate
  lts_ld_125(c_max_nr_chans-1 downto g_nr_chans)     <= (others => '0');
+  lts_ld_rdy_125(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
  lts_cycles_125(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
  lts_tai_125(c_max_nr_chans-1 downto g_nr_chans)    <= (others => (others => '0'));
  lts_wrtag_125(c_max_nr_chans-1 downto g_nr_chans)  <= (others => '0');