Added package file and made adjustments to output enable logic

The main logic changes are that the output enable lines are now set after the internal reset has been spent. This is to make sure that the lines are only controlled by the FPGA and no erroneous glitches are generated. Other changes include the addition of the RTM detection lines to the interface, which are now reflected in the CONV Status Reg, and connecting the reset from register line, which was previously unconnected. Then, component instantiations and the SDB declaration for conv_regs have been moved to the package file (conv_common_gw_pkg).

Added package file and made adjustments to output enable logic
The main logic changes are that the output enable lines are now set after the internal reset has been spent. This is to make sure that the lines are only controlled by the FPGA and no erroneous glitches are generated. Other changes include the addition of the RTM detection lines to the interface, which are now reflected in the CONV Status Reg, and connecting the reset from register line, which was previously unconnected. Then, component instantiations and the SDB declaration for conv_regs have been moved to the package file (conv_common_gw_pkg).
6e1a5f9e · Theodor-Adrian Stana · ff1fc9c5 · 6e1a5f9e · 6e1a5f9e · 6e1a5f9e
Commit 6e1a5f9e authored Aug 01, 2014 by Theodor-Adrian Stana
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Manifest.py top/Manifest.py +2 -1

conv_common_gw.vhd top/conv_common_gw.vhd +61 -299

conv_common_gw_pkg.vhd top/conv_common_gw_pkg.vhd +403 -0

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--- a/top/Manifest.py
+++ b/top/Manifest.py
 files = [
-      "conv_common_gw.vhd"
+      "conv_common_gw.vhd",
+      "conv_common_gw_pkg.vhd"
    ]

 modules = {

--- a/top/conv_common_gw.vhd
+++ b/top/conv_common_gw.vhd
--- a/top/conv_common_gw_pkg.vhd
+++ b/top/conv_common_gw_pkg.vhd