Zynq carrier for RFoWR based application (CITY)

Project description

This card can be used to distribute RF signals over a White Rabbit network.

This board has been developed in order to be used for the ESRF accelerators timing system:

• Bunch injection/extraction, Storage Ring filling
• Beam synchronous triggers for accelerators diagnostic and beamlines experiments

CITY is based on two main design:

• FASEC Zynq SoC design
• FMC DAC 12b 1cha DDS

It is a standalone pizza-box module, enclosed in a 19"1U rack.

The board prototypes are currently under manufacturing. Below is an image of the PCB top view:

Main features

• XC7Z030 controller, SoC with Kintex-7 logic (called PL, i.e. Programmable Logic) and Dual ARM Cortex-A9 MPCore at 1 GHz (called PS, i.e. Processing System)

• 2x Low-Pin Count FMC slots

  • FMC1 connectivity: Vadj fixed to 2.5V, 34 differential pairs, 1 GTP transceiver with clock, 2 clock pairs, JTAG, I2C
  • FMC2 connectivity: Vadj fixed to 1.8V, 34 differential pairs, JTAG, I2C

• FPGA configuration

  • From QSPI flash, Ethernet (through U-Boot bootloader) or MicroSD card

• Clocking resources:

  • SoC:

    • 1x 33.33 MHz fixed oscillator, SoC main clock (clock distribution to PL possible)

  • WR domain:

    • 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)

    • 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)

    • 1x AD9516 frequency synthesizer/fanout: 125MHz WR for WR-PTP core & 500MHz for RFoWR

  • RF domain:

    • 1x ~10-800MHz Programmable VCXO (Si571, custom part: 352MHz center frequency)

    • 1x AD9510 frequency synthesizer/fanout

• On-board memories

  • 2x 512 MByte (4 Gbit) DDR3L (MT41K256M16HA-125:E)

  • 2x 128 Mbit QSPI flash for FPGA bitstream and Linux kernel & root file system storage (S25FL128SAGMFIR01)

• Miscellaneous

  • UCD90120ARGC power controller (programmable over JTAG) to survey power rails and manage power-on and power-off sequence
  • Xilinx-style JTAG connector

• Front panel

  • 1x SMA for RF input (mode master)

  • 1x SMA for RF output (synthesized, slave mode)

  • 1x SMA for user clock output (WR/RF clock multiplexed)

  • 4x LEMO-00 digital input (optional 50 Ohm termination, configurable input voltage threshold)

  • 12x LEMO-00 digital outputs (6 of them have fine delay tuning + RF resynchronization)

  • 1x programmable LED (module status)

• Back panel

  • 1x LEMO connector for WR PPS output

  • 1x BNC connector for WR 10MHz output

  • 1x RJ45 port for 10/100/1000 Mbit Ethernet

  • 1x Micro-USB connector (FT232) for UART console

  • 1x Push button for POR Reset

  • 1x SFP port for WR link

  • 1x SATA connector for GTX user port

• 10-layer PCB

Project information

• Users
• Frequently Asked Questions
• Licenced under CERN OHL V1.2

Contacts

Commercial producers

• not commercially available yet

General questions about project

• Antonin Broquet - ESRF

Status

13 September 2019