This is necessary as hdlmake 2.1 is not working as expect when
generating Vivado project files.

Now, the dsp-cores repository changed the name of the position
calculation core. So, we update it here.

Now, dsp-cores repository employs a new variable in which we
select the machine we want. Currently, we support UVX (130MSPS ADC)
and Sirius (130MSPS ADC).

These cosntraints were missing the correct wildcard "*", in order to be
applied to all input pins. In fact, using wildcard "?" was obviously
applying the constraints only to fmc2_adc3_data_i[0] to fmc2_adc3_data_i[9],
leaving fmc2_adc3_data_i[10] to fmc2_adc3_data_i[15] out

As we have transfered all of the BPM project to
another account, we also update the submodule remotes.

Now, we only have one delta-sigma component instantiation at the FOFB
rate, working iterativelly with one clock cycle per input bit. So, we
need a total of 32 clock cycles, corresponding to 32 input bits.

The FOFB decimation rate is 980, so we could have a CE up to 980/32
and still produce correct results. However, in order to minimize latency
we use the minimum CE avaiable to give an extra timing margin and
still reduce latency. In our case, this value is 2, the ADC CE.

Now, we have the possibility to clock each wb_acq_core module
independently and synchronize everyone to an external memory clock
(ext_clk_i). This should improve the decoupling of FMCs clock trees.

These setting were causing flashing erros in our current boards (AFCv3)

Previously, the RAM current address was read in the same
cycle as STB and CYC. As the default Wishbone signals are
0's, the RAM read address was 0, which its contents are 0's
for this module.

As the RAM takes one clock cycle to return the requested data,
the Wishbone data output was reading the previous RAM data, which
corresponds to the data in RAM address 0.

This was happening regardless of the Wishbone address and the
Wishbone data output was always one clock cycle too late, which
is not interpreted as valid by the Wishbone Crossbar Switch module.

This module recives some information (uTCA board ID, uTCA slot
number and some sensor readings) from LPC via SPI.