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Beam Positoning Monitor - Gateware
Commit 73a14c12 authored by Lucas Russo's avatar Lucas Russo
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hdl/top/afc_v3/vivado/test_adc_clk/*: add simple FMC clock test

parent 2a3a24fe
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hdl/top/afc_v3/vivado/test_adc_clk/Manifest.py 0 → 100644
View file @ 73a14c12
files = [ "dbe_bpm_dsp.vhd",
"dbe_bpm_dsp.xdc"];
modules = { "local" :
["../../../..",
"../../../../ip_cores/pcie/7a200ffg1156"
]
};
hdl/top/afc_v3/vivado/test_adc_clk/dbe_bpm_dsp.vhd 0 → 100755
View file @ 73a14c12
------------------------------------------------------------------------------
-- Title : Top DSP design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-09-01
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top design for testing the integration/control of the DSP with
-- FMC130M_4ch board
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-09-01 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity dbe_bpm_dsp is
port(
-----------------------------
-- FMC1_130m_4ch ports
-----------------------------
-- ADC0 LTC2208
fmc1_adc0_clk_i : in std_logic;
-- FMC LEDs
fmc1_led1_o : out std_logic;
fmc1_led2_o : out std_logic;
fmc1_led3_o : out std_logic;
-----------------------------
-- FMC2_130m_4ch ports
-----------------------------
-- ADC0 LTC2208
fmc2_adc0_clk_i : in std_logic;
-- FMC LEDs
fmc2_led1_o : out std_logic;
fmc2_led2_o : out std_logic;
fmc2_led3_o : out std_logic
);
end dbe_bpm_dsp;
architecture rtl of dbe_bpm_dsp is
constant c_max_count : natural := 113000000;
signal fmc1_adc0_clk_buf : std_logic;
signal fmc2_adc0_clk_buf : std_logic;
signal fmc1_adc0_clk_bufg : std_logic;
signal fmc2_adc0_clk_bufg : std_logic;
begin
cmp_ibuf_adc1_clk0 : ibuf
generic map(
IOSTANDARD => "LVCMOS25"
)
port map(
i => fmc1_adc0_clk_i,
o => fmc1_adc0_clk_buf
);
cmp_bufg_adc1_clk0 : BUFG
port map(
O => fmc1_adc0_clk_bufg,
I => fmc1_adc0_clk_buf
);
cmp_ibuf_adc2_clk0 : ibuf
generic map(
IOSTANDARD => "LVCMOS25"
)
port map(
i => fmc2_adc0_clk_i,
o => fmc2_adc0_clk_buf
);
cmp_bufg_adc2_clk0 : BUFG
port map(
O => fmc2_adc0_clk_bufg,
I => fmc2_adc0_clk_buf
);
p_counter1 : process(fmc1_adc0_clk_bufg)
variable count : natural range 0 to c_max_count;
begin
if rising_edge(fmc1_adc0_clk_bufg) then
if count < c_max_count/2 then
count := count + 1;
fmc1_led1_o <= '1';
elsif count < c_max_count then
fmc1_led1_o <= '0';
count := count + 1;
else
fmc1_led1_o <= '1';
count := 0;
end if;
end if;
end process;
fmc1_led2_o <= '0';
fmc1_led3_o <= '0';
p_counter2 : process(fmc2_adc0_clk_bufg)
variable count : natural range 0 to c_max_count;
begin
if rising_edge(fmc2_adc0_clk_bufg) then
if count < c_max_count/2 then
count := count + 1;
fmc2_led1_o <= '1';
elsif count < c_max_count then
fmc2_led1_o <= '0';
count := count + 1;
else
fmc2_led1_o <= '1';
count := 0;
end if;
end if;
end process;
fmc2_led2_o <= '0';
fmc2_led3_o <= '0';
end rtl;
hdl/top/afc_v3/vivado/test_adc_clk/dbe_bpm_dsp.xdc 0 → 100644
View file @ 73a14c12
#######################################################################
## Artix 7 AMC V3 ##
#######################################################################
#######################################################################
## FMC Connector HPC1 ##
#######################################################################
#// LEDs
#// LA16_N
set_property PACKAGE_PIN L9 [get_ports fmc1_led1_o]
set_property IOSTANDARD LVCMOS25 [get_ports fmc1_led1_o]
#// LA16_P
set_property PACKAGE_PIN L10 [get_ports fmc1_led2_o]
set_property IOSTANDARD LVCMOS25 [get_ports fmc1_led2_o]
#// LA26_P
set_property PACKAGE_PIN T2 [get_ports fmc1_led3_o]
set_property IOSTANDARD LVCMOS25 [get_ports fmc1_led3_o]
#######################################################################
## FMC Connector HPC2 ##
#######################################################################
#// LEDs
#// LA16_N
set_property PACKAGE_PIN AD34 [get_ports fmc2_led1_o]
set_property IOSTANDARD LVCMOS25 [get_ports fmc2_led1_o]
#// LA16_P
set_property PACKAGE_PIN AD33 [get_ports fmc2_led2_o]
set_property IOSTANDARD LVCMOS25 [get_ports fmc2_led2_o]
#// LA26_P
set_property PACKAGE_PIN AC32 [get_ports fmc2_led3_o]
set_property IOSTANDARD LVCMOS25 [get_ports fmc2_led3_o]
#######################################################################
## FMC Connector HPC1 #
## LTC ADC lines #
#######################################################################
#// ADC0
#// LA17_CC_P
set_property PACKAGE_PIN T5 [get_ports fmc1_adc0_clk_i]
set_property IOSTANDARD LVCMOS25 [get_ports fmc1_adc0_clk_i]
#######################################################################
## FMC Connector HPC2 #
## LTC ADC lines #
#######################################################################
#// ADC0
#// LA17_CC_P
set_property PACKAGE_PIN AB31 [get_ports fmc2_adc0_clk_i]
set_property IOSTANDARD LVCMOS25 [get_ports fmc2_adc0_clk_i]
#######################################################################
## Clocks ##
#######################################################################
# real jitter is about 22ps peak-to-peak
create_clock -period 8.000 -name fmc1_adc0_clk_i [get_ports fmc1_adc0_clk_i]
set_input_jitter fmc1_adc0_clk_i 0.050
create_clock -period 8.000 -name fmc2_adc0_clk_i [get_ports fmc2_adc0_clk_i]
set_input_jitter fmc2_adc0_clk_i 0.050
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