- 30 Oct, 2017 2 commits
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Lucas Russo authored
In this way, we can save FPGA resources, as all acquisition transactions from Post-Mortem are done via the external DDR.
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Lucas Russo authored
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- 11 Sep, 2017 1 commit
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Lucas Russo authored
Ever since we began using the infra_cores submodule, the related SDB record is missing from the top SDB layout.
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- 30 Aug, 2017 1 commit
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Lucas Russo authored
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- 28 Aug, 2017 3 commits
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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- 25 Aug, 2017 3 commits
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Lucas Russo authored
Not sure why this happens, but this workaround seems to work ok.
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Lucas Russo authored
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Lucas Russo authored
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- 23 Aug, 2017 1 commit
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Lucas Russo authored
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- 22 Aug, 2017 1 commit
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Lucas Russo authored
We must not count the special meta records in the number of slaves. These will issue an error in recent xwb_sdb_crossbar implementations.
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- 08 Aug, 2017 1 commit
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Lucas Russo authored
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- 07 Aug, 2017 3 commits
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Lucas Russo authored
As dsp-cores commit e2d16e4c36 changed mixer width, we need to change it here. We need to be caution here anyway, as a change in the mixer width will not reflect to a change in the acquisition core mixer width. Fix for this is pending.
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Lucas Russo authored
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Lucas Russo authored
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- 03 Aug, 2017 1 commit
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Lucas Russo authored
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- 02 Aug, 2017 3 commits
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Lucas Russo authored
All of this files are already present in infra-cores repo. So, no need to keep them here.
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Lucas Russo authored
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Lucas Russo authored
This infra-cores repo is a cut from this repository that contains a cut from general modules developed in the context of the BPM project.
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- 24 Jul, 2017 2 commits
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Lucas Russo authored
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Lucas Russo authored
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- 21 Jul, 2017 6 commits
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Lucas Russo authored
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Lucas Russo authored
In this way, we can reset MMCM by software
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Lucas Russo authored
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Lucas Russo authored
This will be used manually reset the ADC MMCM by software, every time a clock change happens.
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Lucas Russo authored
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Lucas Russo authored
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- 20 Jul, 2017 1 commit
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Lucas Russo authored
Now, on asserting LOCKED by MMCM, we synchronize it to the destination clock domain and waits until the LOCK signal has stabilized for a few clock cycles. In this way we can safely use the mmcm_adc_locked signal as a reset to downstream logic.
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- 18 Jul, 2017 1 commit
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Lucas Russo authored
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- 12 Jul, 2017 2 commits
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Lucas Russo authored
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Lucas Russo authored
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- 10 Jul, 2017 2 commits
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Lucas Russo authored
Even though we don't have much CORDIC iterations to yield a good resolution, it's good to be able to acquire the phase for debugging purposes.
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Lucas Russo authored
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- 04 Jul, 2017 1 commit
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Lucas Russo authored
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- 27 Jun, 2017 2 commits
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Lucas Russo authored
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Lucas Russo authored
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- 22 Jun, 2017 1 commit
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Lucas Russo authored
This is a more semantic name.
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- 20 Jun, 2017 2 commits
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Lucas Russo authored
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Lucas Russo authored
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