Hdlmake support for simulation

e8a0063e · Adrian Byszuk · 1ecfa6ef · e8a0063e · e8a0063e · e8a0063e
Commit e8a0063e authored Jan 04, 2013 by Adrian Byszuk
6 changed files
--- a/hdl/ip_cores/pcie/7k325ffg900/Manifest.py
+++ b/hdl/ip_cores/pcie/7k325ffg900/Manifest.py
 if (action == "synthesis"):

-    modules = {"local" : ["pcie_core/source"]}
-
    files = ["bram_x64.ngc",
             "eb_fifo_counted_resized.ngc",
             "mbuf_128x72.ngc",
@@ -15,3 +13,5 @@ else:
             "mbuf_128x72.vhd",
             "prime_FIFO_plain.vhd",
             "sfifo_15x128.vhd"]
+
+modules = {"local" : ["pcie_core/source"]}
--- a/hdl/sim/pcie/Manifest.py
+++ b/hdl/sim/pcie/Manifest.py
+files = ["pci_exp_usrapp_cfg.v",
+         "pci_exp_usrapp_com.v",
+         "pci_exp_usrapp_pl.v",
+         "pci_exp_usrapp_rx.v",
+         "pci_exp_usrapp_tx.v",
+         "pcie_2_1_rport_7x.v",
+         "pcie_axi_trn_bridge.v",
+         "xilinx_pcie_2_1_rport_7x.v",
+         "sys_clk_gen.v",
+         "sys_clk_gen_ds.v"]
--- a/hdl/testbench/pcie/sample_tests1.v
+++ b/hdl/testbench/pcie/sample_tests1.v
--- a/hdl/testbench/pcie/tests.v
+++ b/hdl/testbench/pcie/tests.v
--- a/hdl/testbench/pcie/Makefile
+++ b/hdl/testbench/pcie/Makefile
--- a/hdl/testbench/pcie/Manifest.py
+++ b/hdl/testbench/pcie/Manifest.py
+import os as __os
+import shutil as __shutil
+
+def __import_verilog_lib():
+	xilinx_dir = __os.getenv("XILINX");
+	if xilinx_dir == None:
+		print("XILINX variable not set")
+		__os.exit(-1)
+
+	if __os.path.isdir("work"):
+		return
+
+	verilog_lib = xilinx_dir + "/ISE/verilog/src/glbl.v"
+	print("Copying " + verilog_lib)
+	#__os.mkdir("work")
+	__shutil.copy(verilog_lib, ".")
+
+
 target = "xilinx"
 action = "simulation"
+vlog_opt = "-i ../../sim/pcie -d SIMULATION"
+# ENABLE_GT has to be set until I figure out a way
+# to force ISIM to work in PIPE simulation mode
+vlog_opt += " -d ENABLE_GT"
+vsim_opt = "-testplusarg TESTNAME=tf64_pcie_axi"
+
+__import_verilog_lib()
+files = ["board.v",
+         "glbl.v"]

-syn_project = "bpm_pcie_sim.xise"
 #top_module = "tf64_pcie_axi"
 modules = {"local" : ["../../modules/pcie",
-                      "../../ip_cores/pcie/7k325ffg900"]}
+                      "../../ip_cores/pcie/7k325ffg900",
+                      "../../sim/pcie",
+                      "../../top/pcie"]}

-files = "tf64_pcie_axi.v"