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Beam Positoning Monitor - Gateware
Commit 1ecfa6ef authored by Adrian Byszuk's avatar Adrian Byszuk
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Prepare to support PCIE core v1.8 PIPE simulation mode

parent a89154fe
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Showing with 510 additions and 8 deletions
hdl/sim/pcie/pcie_2_1_rport_7x.v
View file @ 1ecfa6ef
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hdl/testbench/pcie/board.v
View file @ 1ecfa6ef
......@@ -131,10 +131,20 @@ wire [0:0] rp_pci_exp_txp;
//
// PCI-Express Endpoint Instance
//
`ifdef ENABLE_GT
parameter PIPE_SIM = "FALSE";
parameter PIPE_SIM_MODE = "FALSE";
defparam board.RP.rport.PIPE_SIM_MODE = "FALSE";
`else
parameter PIPE_SIM = "TRUE";
parameter PIPE_SIM_MODE = "TRUE";
defparam board.RP.rport.PIPE_SIM_MODE = "TRUE";
`endif
bpm_pcie_k7 # (
.PL_FAST_TRAIN("TRUE")
.PL_FAST_TRAIN("TRUE"),
.PIPE_SIM_MODE(PIPE_SIM_MODE)
)
EP (
......@@ -238,6 +248,8 @@ CLK_GEN_EP (
end
end
`include "pipe_interconnect.v"
initial begin
$display("[%t] : System Reset Asserted...", $realtime);
......
hdl/testbench/pcie/board_vlog.f
View file @ 1ecfa6ef
......@@ -29,6 +29,7 @@ board.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_wrapper.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_rx_valid_filter_7x.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_top.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_top_pipe_mode.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_bram_top_7x.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_brams_7x.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_bram_7x.v
......
hdl/testbench/pcie/pipe_interconnect.v 0 → 100644
View file @ 1ecfa6ef
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pipe_interconnect.v
// Version : 1.7
`define EP board.EP.pcie_core_i.pcie_top_i
`define RP board.RP.rport.pcie_top_i
//---------------------------------------------------------- PIO RTL & RP simulation -------------------------------------------------------------------//
generate
if (PIPE_SIM == "TRUE")
begin
assign `EP.pipe_rx0_char_is_k_gt = `RP.pipe_tx0_char_is_k_gt;
assign `EP.pipe_rx1_char_is_k_gt = `RP.pipe_tx1_char_is_k_gt;
assign `EP.pipe_rx2_char_is_k_gt = `RP.pipe_tx2_char_is_k_gt;
assign `EP.pipe_rx3_char_is_k_gt = `RP.pipe_tx3_char_is_k_gt;
assign `EP.pipe_rx4_char_is_k_gt = `RP.pipe_tx4_char_is_k_gt;
assign `EP.pipe_rx5_char_is_k_gt = `RP.pipe_tx5_char_is_k_gt;
assign `EP.pipe_rx6_char_is_k_gt = `RP.pipe_tx6_char_is_k_gt;
assign `EP.pipe_rx7_char_is_k_gt = `RP.pipe_tx7_char_is_k_gt;
assign `EP.pipe_rx0_data_gt = `RP.pipe_tx0_data_gt;
assign `EP.pipe_rx1_data_gt = `RP.pipe_tx1_data_gt;
assign `EP.pipe_rx2_data_gt = `RP.pipe_tx2_data_gt;
assign `EP.pipe_rx3_data_gt = `RP.pipe_tx3_data_gt;
assign `EP.pipe_rx4_data_gt = `RP.pipe_tx4_data_gt;
assign `EP.pipe_rx5_data_gt = `RP.pipe_tx5_data_gt;
assign `EP.pipe_rx6_data_gt = `RP.pipe_tx6_data_gt;
assign `EP.pipe_rx7_data_gt = `RP.pipe_tx7_data_gt;
//-------------------------------------------------------------------------------------------------------------------------//
assign `RP.pipe_rx0_char_is_k_gt = `EP.pipe_tx0_char_is_k_gt;
assign `RP.pipe_rx1_char_is_k_gt = `EP.pipe_tx1_char_is_k_gt;
assign `RP.pipe_rx2_char_is_k_gt = `EP.pipe_tx2_char_is_k_gt;
assign `RP.pipe_rx3_char_is_k_gt = `EP.pipe_tx3_char_is_k_gt;
assign `RP.pipe_rx4_char_is_k_gt = `EP.pipe_tx4_char_is_k_gt;
assign `RP.pipe_rx5_char_is_k_gt = `EP.pipe_tx5_char_is_k_gt;
assign `RP.pipe_rx6_char_is_k_gt = `EP.pipe_tx6_char_is_k_gt;
assign `RP.pipe_rx7_char_is_k_gt = `EP.pipe_tx7_char_is_k_gt;
assign `RP.pipe_rx0_data_gt = `EP.pipe_tx0_data_gt;
assign `RP.pipe_rx1_data_gt = `EP.pipe_tx1_data_gt;
assign `RP.pipe_rx2_data_gt = `EP.pipe_tx2_data_gt;
assign `RP.pipe_rx3_data_gt = `EP.pipe_tx3_data_gt;
assign `RP.pipe_rx4_data_gt = `EP.pipe_tx4_data_gt;
assign `RP.pipe_rx5_data_gt = `EP.pipe_tx5_data_gt;
assign `RP.pipe_rx6_data_gt = `EP.pipe_tx6_data_gt;
assign `RP.pipe_rx7_data_gt = `EP.pipe_tx7_data_gt;
end
endgenerate
//----------------------------------------------------------------------------------------------------------------------------------------------------------//
hdl/testbench/pcie/simulate_isim.sh
View file @ 1ecfa6ef
......@@ -4,12 +4,13 @@
TEST=tf64_pcie_axi
# compile all of the files
vlogcomp -work work -d SIMULATION -i . -i ../../sim/pcie --incremental -f board_vlog.f && \
# Include -d ENABLE_GT to run the simulations in GT mode
vlogcomp -work work -d ENABLE_GT -d SIMULATION -i . -i ../../sim/pcie --incremental -f board_vlog.f && \
vhpcomp -work work --incremental -f board.f && \
vlogcomp -work work $XILINX/verilog/src/glbl.v && \
# compile and link source files
fuse work.board work.glbl -L unisims_ver -L unimacro_ver -L unisim -L unimacro -L secureip -o tb_sim
fuse work.board work.glbl -d ENABLE_GT -d SIMULATION -L unisims_ver -L unimacro_ver -L unisim -L unimacro -L secureip -o tb_sim
# set BATCH_MODE=0 to run simulation in GUI mode
BATCH_MODE=0
......
hdl/testbench/pcie/tf64_pcie_axi.v
View file @ 1ecfa6ef
......@@ -932,7 +932,7 @@ begin
//////////////////////////////////////////////////////////////////////////////////
TSK_CLK_EAT(100);
TSK_TX_CLK_EAT(100);
$display("### Simulation FINISHED ###\n");
$finish(2);
......
hdl/top/pcie/bpm_pcie_k7.vhd
View file @ 1ecfa6ef
......@@ -35,7 +35,8 @@ use UNISIM.VComponents.all;
entity bpm_pcie_k7 is
generic (
constant pcieLanes : integer := C_NUM_PCIE_LANES;
PL_FAST_TRAIN : string := "FALSE"
PL_FAST_TRAIN : string := "FALSE";
PIPE_SIM_MODE : string := "FALSE"
);
port (
......@@ -67,7 +68,8 @@ architecture Behavioral of bpm_pcie_k7 is
generic (
PL_FAST_TRAIN : string := "FALSE";
PCIE_EXT_CLK : string := "FALSE";
UPSTREAM_FACING : string := "TRUE"
UPSTREAM_FACING : string := "TRUE";
PIPE_SIM_MODE : string := "FALSE"
);
port (
-------------------------------------------------------------------------------------------------------------------
......@@ -1299,7 +1301,8 @@ begin
pcie_core_i : pcie_core
generic map(
PL_FAST_TRAIN => PL_FAST_TRAIN,
PCIE_EXT_CLK => "FALSE"
PCIE_EXT_CLK => "FALSE",
PIPE_SIM_MODE => "FALSE"
)
port map(
--------------------------------------------------------------------------------------------------------------------
......
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