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Beam Positoning Monitor - Gateware
Commit be11df22 authored by Adrian Byszuk's avatar Adrian Byszuk
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Merge branch pcie_sim-devel & update Root Port model to v1.8

parents e83be099 44e4a12f
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hdl/ip_cores/pcie/7k325ffg900/Manifest.py
View file @ be11df22
if (action == "synthesis"):
modules = {"local" : ["pcie_core/source"]}
files = ["bram_x64.ngc",
"eb_fifo_counted_resized.ngc",
"mbuf_128x72.ngc",
......@@ -15,3 +13,5 @@ else:
"mbuf_128x72.vhd",
"prime_FIFO_plain.vhd",
"sfifo_15x128.vhd"]
modules = {"local" : ["pcie_core/source"]}
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_top.v
View file @ be11df22
......@@ -251,8 +251,8 @@ module pcie_core_gt_top #
localparam PCIE_LINK_SPEED = (PL_FAST_TRAIN == "TRUE") ? 2 : 3;
// The parameter PCIE_OOBCLK_MODE_ENABLE value should be "0" for simulation and for synthesis it should be 1
//localparam PCIE_OOBCLK_MODE_ENABLE = (PL_FAST_TRAIN == "TRUE") ? 0 : 1;
localparam PCIE_OOBCLK_MODE_ENABLE = 1;
localparam PCIE_OOBCLK_MODE_ENABLE = (PL_FAST_TRAIN == "TRUE") ? 0 : 1;
//localparam PCIE_OOBCLK_MODE_ENABLE = 1;
localparam PCIE_TX_EIDLE_ASSERT_DELAY = (PL_FAST_TRAIN == "TRUE") ? 4 : 2;
......
hdl/modules/pcie/common/tx_Mem_Reader.vhd
View file @ be11df22
......@@ -723,7 +723,7 @@ begin
else eb_FIFO_qout_shift when (eb_FIFO_Hit = '1' and Shift_1st_QWord_k = '1')
else (others => '0');
DDR_Dout_wire <= DDR_FIFO_RdQout when DDR_FIFO_Hit = '1' else (others => '0');
Regs_RdQout_wire <= Regs_RdQout(31 downto 0) & Regs_RdQout(63 downto 32) --watch out!
Regs_RdQout_wire <= Regs_RdQout --watch out!
when Regs_Hit = '1' else (others => '0');
mbuf_Din_wire_OR <= eb_FIFO_Dout_wire or DDR_Dout_wire or Regs_RdQout_wire;
......
hdl/modules/pcie/common/tx_Transact.vhd
View file @ be11df22
......@@ -386,8 +386,8 @@ begin
-- Always deasserted
s_axis_tx_tdsc_i <= '1';
s_axis_tx_terrfwd_i <= '1';
s_axis_tx_tdsc_i <= '0';
s_axis_tx_terrfwd_i <= '0';
-- s_axis_tx_tkeep_i <= (OTHERS=>'0');
......@@ -1070,7 +1070,7 @@ begin
mbuf_RE_ok <= '1';
else -- 3DW header
-- s_axis_tx_tdata_i <= Trn_Qout_reg (C_DBUS_WIDTH-1+64 downto 64);
s_axis_tx_tdata_i <= mbuf_Qout(C_DBUS_WIDTH-1-32 downto 0)
s_axis_tx_tdata_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 32)
& Trn_Qout_reg (C_DBUS_WIDTH+32-1 downto C_DBUS_WIDTH);
trn_tsof_n_i <= '1';
s_axis_tx_tlast_i <= not(mbuf_Qout(C_DBUS_WIDTH));
......
hdl/sim/pcie/Manifest.py 0 → 100644
View file @ be11df22
files = ["pci_exp_usrapp_cfg.v",
"pci_exp_usrapp_com.v",
"pci_exp_usrapp_pl.v",
"pci_exp_usrapp_rx.v",
"pci_exp_usrapp_tx.v",
"pcie_2_1_rport_7x.v",
"pcie_axi_trn_bridge.v",
"xilinx_pcie_2_1_rport_7x.v",
"sys_clk_gen.v",
"sys_clk_gen_ds.v"]
hdl/sim/pcie/board_common.v 0 → 100644
View file @ be11df22
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : board_common.v
// Version : 1.8
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
`define IO_TRUE 1
`define IO_FALSE 0
`define TX_TASKS board.RP.tx_usrapp
// Endpoint Sys clock clock frequency 100 MHz -> half clock -> 5000 pS
`define SYS_CLK_COR_HALF_CLK_PERIOD 5000
// Downstrean Port Sys clock clock frequency 250 MHz -> half clock -> 2000 pS
`define SYS_CLK_DSPORT_HALF_CLK_PERIOD 2000
`define RX_LOG 0
`define TX_LOG 1
// PCI Express TLP Types constants
`define PCI_EXP_MEM_READ32 7'b0000000
`define PCI_EXP_IO_READ 7'b0000010
`define PCI_EXP_CFG_READ0 7'b0000100
`define PCI_EXP_COMPLETION_WO_DATA 7'b0001010
`define PCI_EXP_MEM_READ64 7'b0100000
`define PCI_EXP_MSG_NODATA 7'b0110xxx
`define PCI_EXP_MEM_WRITE32 7'b1000000
`define PCI_EXP_IO_WRITE 7'b1000010
`define PCI_EXP_CFG_WRITE0 7'b1000100
`define PCI_EXP_COMPLETION_DATA 7'b1001010
`define PCI_EXP_MEM_WRITE64 7'b1100000
`define PCI_EXP_MSG_DATA 7'b1110xxx
`define TRN_RX_TIMEOUT 5000
hdl/sim/pcie/helper_tasks.v 0 → 100644
View file @ be11df22
//////////////////
// tf64_pcie_exi defines
/////////////////
//`define RANDOM_SEQUENCE
/* Time parameters */
`define T_DELAY_AFTER 0.0
`define T_DELTA 0.1
`define T_PIO_INTERVAL 50.0
`define T_DMA_INTERVAL 300.0
`define T_RX_NO_FC_PERIOD 1900000.0
`define T_TX_NO_FC_PERIOD 1500000.0
/* Memory size for simulation */
`define C_ARRAY_DIMENSION 4096
/* Start indices */
`define PIO_START_INDEX 'H0300
`define DMA_START_INDEX 'H0000
/* Request completion boundary */
`define C_RCB_16_DW 'H10
`define C_RCB_32_DW 'H20
/* BAR */
`define C_BAR0_HIT 7'H01
`define C_BAR1_HIT 7'H02
`define C_BAR2_HIT 7'H03
`define C_BAR3_HIT 7'H04
`define C_BAR4_HIT 7'H05
`define C_BAR5_HIT 7'H06
`define C_BAR6_HIT 7'H07
`define C_NO_BAR_HIT 7'H00
/* Requester ID and Completer ID */
`define C_HOST_WRREQ_ID 16'H0ABC
`define C_HOST_RDREQ_ID 16'HE1E2
`define C_HOST_CPLD_ID 16'HC01D
/* 1st header */
`define HEADER0_MWR3_ 32'H40000000
`define HEADER0_MWR4_ 32'H60000000
`define HEADER0_MRD3_ 32'H00000000
`define HEADER0_MRD4_ 32'H20000000
`define HEADER0_CPLD 32'H4A000000
`define HEADER0_CPL 32'H0A000000
`define HEADER0_MSG 32'H34000001
/* Message codes */
`define C_MSG_CODE_INTA 8'H20
`define C_MSG_CODE_INTA_N 8'H24
/* Payload type */
`define USE_PRIVATE 1
`define USE_PUBLIC 0
/* General registers */
`define C_ADDR_VERSION 32'H0000
`define C_ADDR_IRQ_STAT 32'H0008
`define C_ADDR_IRQ_EN 32'H0010
`define C_ADDR_GSR 32'H0020
`define C_ADDR_GCR 32'H0028
/* Control registers for special ports */
`define C_ADDR_MRD_CTRL 32'H0074
`define C_ADDR_TX_CTRL 32'H0078
`define C_ADDR_ICAP 32'H007C
`define C_ADDR_EB_STACON 32'H0090
/* Downstream DMA channel registers */
`define C_ADDR_DMA_DS_PAH 32'H0050
`define C_ADDR_DMA_DS_CTRL 32'H006C
`define C_ADDR_DMA_DS_STA 32'H0070
/* Upstream DMA channel registers */
`define C_ADDR_DMA_US_PAH 32'H002C
`define C_ADDR_DMA_US_CTRL 32'H0048
`define C_ADDR_DMA_US_STA 32'H004C
/* DMA-specific constants */
`define C_DMA_RST_CMD 32'H0200000A
// ***************************************** //
// Tasks //
// ***************************************** //
task dword_pack_data_store;
input [31:0] dword;
input [10:0] offset;
begin
board.RP.tx_usrapp.DATA_STORE[offset*4 + 3] = dword[31:24];
board.RP.tx_usrapp.DATA_STORE[offset*4 + 2] = dword[23:16];
board.RP.tx_usrapp.DATA_STORE[offset*4 + 1] = dword[15:8];
board.RP.tx_usrapp.DATA_STORE[offset*4 + 0] = dword[7:0];
end
endtask //dword_pack_data_store
///////////////////////////////////////////////
// Copy random data to tx send buffer //
///////////////////////////////////////////////
task Copy_rnd_data;
reg [7:0] i;
begin
for (i = 0; i <= 100; i = i + 1) begin
board.RP.tx_usrapp.DATA_STORE[i*4 + 3] = board.D_Array[i][31:24];
board.RP.tx_usrapp.DATA_STORE[i*4 + 2] = board.D_Array[i][23:16];
board.RP.tx_usrapp.DATA_STORE[i*4 + 1] = board.D_Array[i][15:8];
board.RP.tx_usrapp.DATA_STORE[i*4 + 0] = board.D_Array[i][7:0];
end
end
endtask // Copy_rnd_data
///////////////////////////////////////////////
// //
// Feed TLP to Rx: MRd, MWr, Cpl/D, Msg //
// //
///////////////////////////////////////////////
task TLP_Feed_Rx;
input [ 6:0] BAR_Hit_N; // Which BAR is hit
reg [63:0] sys_addr;
reg [31:0] hdr_type;
reg [31:0] hdr_mask;
begin
hdr_mask = 32'hFF000000;
sys_addr = board.RP.tx_usrapp.BAR_INIT_P_BAR[BAR_Hit_N - 1] +
board.Hdr_Array[2];
hdr_type = board.Hdr_Array[0] & hdr_mask;
if ((board.Hdr_Array[0] & 32'hFF000000) == `HEADER0_MWR4_) begin
board.RP.tx_usrapp.TSK_TX_MEMORY_WRITE_64(board.Hdr_Array[1][15:8],
board.Hdr_Array[0][22:20],
board.Hdr_Array[0][9:0],
sys_addr,
board.Hdr_Array[0][7:4],
board.Hdr_Array[0][3:0],
0);
end
else if ((board.Hdr_Array[0] & 32'hFF000000) == `HEADER0_MWR3_) begin
board.RP.tx_usrapp.TSK_TX_MEMORY_WRITE_32(board.Hdr_Array[1][15:8],
board.Hdr_Array[0][22:20],
board.Hdr_Array[0][9:0],
sys_addr[31:0],
board.Hdr_Array[0][7:4],
board.Hdr_Array[0][3:0],
0);
end
else if ((board.Hdr_Array[0] & 32'hFF000000) == `HEADER0_MRD4_) begin
board.RP.tx_usrapp.TSK_TX_MEMORY_READ_64(board.Hdr_Array[1][15:8],
board.Hdr_Array[0][22:20],
board.Hdr_Array[0][9:0],
sys_addr,
board.Hdr_Array[0][7:4],
board.Hdr_Array[0][3:0]);
end
else if ((board.Hdr_Array[0] & 32'hFF000000) == `HEADER0_MRD3_) begin
board.RP.tx_usrapp.TSK_TX_MEMORY_READ_32(board.Hdr_Array[1][15:8],
board.Hdr_Array[0][22:20],
board.Hdr_Array[0][9:0],
sys_addr[31:0],
board.Hdr_Array[0][7:4],
board.Hdr_Array[0][3:0]);
end
else if ((board.Hdr_Array[0] & 32'hFF000000) == `HEADER0_CPLD) begin
board.RP.tx_usrapp.TSK_TX_COMPLETION_DATA(board.Hdr_Array[2][15:8],
board.Hdr_Array[0][22:20],
board.Hdr_Array[0][9:0],
board.Hdr_Array[1][11:0],
board.Hdr_Array[2][6:0],
board.Hdr_Array[1][15:13],
0);
end
else if ((board.Hdr_Array[0] & 32'hFF000000) == `HEADER0_CPL) begin
board.RP.tx_usrapp.TSK_TX_COMPLETION(board.Hdr_Array[2][15:8],
board.Hdr_Array[0][22:20],
board.Hdr_Array[0][9:0],
board.Hdr_Array[1][15:13]);
end
else if ((board.Hdr_Array[0] & 32'hFF000000) == `HEADER0_MSG) begin
board.RP.tx_usrapp.TSK_TX_MESSAGE(board.Hdr_Array[1][15:8],
board.Hdr_Array[0][22:20],
board.Hdr_Array[0][9:0],
0, //board.RP.tx_usrapp.DATA_STORE[7:0],
board.Hdr_Array[0][26:24],
board.Hdr_Array[1][7:0]);
end
else begin
$display("%d ns: TLP_Feed_Rx: unknown header type!", $time);
#10 $finish;
end
end
endtask
/////////////////////////////////////////////
// //
// Function - Endian Inversion 64-bit //
// //
/////////////////////////////////////////////
function [31:00] Inv_Endian;
input [31:00] Data;
begin
Inv_Endian = {Data[ 7: 0], Data[15: 8], Data[23:16], Data[31:24]};
end
endfunction
hdl/sim/pcie/pci_exp_expect_tasks.v 0 → 100644
View file @ be11df22
This diff is collapsed.
hdl/sim/pcie/pci_exp_usrapp_cfg.v 0 → 100644
View file @ be11df22
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pci_exp_usrapp_cfg.v
// Version : 1.8
//--
//--------------------------------------------------------------------------------
`include "board_common.v"
module pci_exp_usrapp_cfg (
cfg_do,
cfg_di,
cfg_byte_en_n,
cfg_dwaddr,
cfg_wr_en_n,
cfg_rd_en_n,
cfg_rd_wr_done_n,
cfg_err_cor_n,
cfg_err_ur_n,
cfg_err_ecrc_n,
cfg_err_cpl_timeout_n,
cfg_err_cpl_abort_n,
cfg_err_cpl_unexpect_n,
cfg_err_posted_n,
cfg_err_tlp_cpl_header,
cfg_interrupt_n,
cfg_interrupt_rdy_n,
cfg_turnoff_ok_n,
cfg_to_turnoff_n,
cfg_bus_number,
cfg_device_number,
cfg_function_number,
cfg_status,
cfg_command,
cfg_dstatus,
cfg_dcommand,
cfg_lstatus,
cfg_lcommand,
cfg_pcie_link_state_n,
cfg_trn_pending_n,
cfg_pm_wake_n,
trn_clk,
trn_reset_n
);
input [(32 - 1):0] cfg_do;
output [(32 - 1):0] cfg_di;
output [(32/8 - 1):0] cfg_byte_en_n;
output [(10 - 1):0] cfg_dwaddr;
output cfg_wr_en_n;
output cfg_rd_en_n;
input cfg_rd_wr_done_n;
output cfg_err_cor_n;
output cfg_err_ur_n;
output cfg_err_ecrc_n;
output cfg_err_cpl_timeout_n;
output cfg_err_cpl_abort_n;
output cfg_err_cpl_unexpect_n;
output cfg_err_posted_n;
output [(48 - 1):0] cfg_err_tlp_cpl_header;
output cfg_interrupt_n;
input cfg_interrupt_rdy_n;
output cfg_turnoff_ok_n;
input cfg_to_turnoff_n;
output cfg_pm_wake_n;
input [(8 - 1):0] cfg_bus_number;
input [(5 - 1):0] cfg_device_number;
input [(3 - 1):0] cfg_function_number;
input [(16 - 1):0] cfg_status;
input [(16- 1):0] cfg_command;
input [(16- 1):0] cfg_dstatus;
input [(16 - 1):0] cfg_dcommand;
input [(16 - 1):0] cfg_lstatus;
input [(16 - 1):0] cfg_lcommand;
input [(3 - 1):0] cfg_pcie_link_state_n;
output cfg_trn_pending_n;
input trn_clk;
input trn_reset_n;
parameter Tcq = 1;
reg [(32 - 1):0] cfg_di;
reg [(32/8 - 1):0] cfg_byte_en_n;
reg [(10 - 1):0] cfg_dwaddr;
reg cfg_wr_en_n;
reg cfg_rd_en_n;
reg cfg_err_cor_n;
reg cfg_err_ecrc_n;
reg cfg_err_ur_n;
reg cfg_err_cpl_timeout_n;
reg cfg_err_cpl_abort_n;
reg cfg_err_cpl_unexpect_n;
reg cfg_err_posted_n;
reg [(48 - 1):0] cfg_err_tlp_cpl_header;
reg cfg_interrupt_n;
reg cfg_turnoff_ok_n;
reg cfg_pm_wake_n;
reg cfg_trn_pending_n;
initial begin
cfg_err_cor_n <= 1'b1;
cfg_err_ur_n <= 1'b1;
cfg_err_ecrc_n <= 1'b1;
cfg_err_cpl_timeout_n <= 1'b1;
cfg_err_cpl_abort_n <= 1'b1;
cfg_err_cpl_unexpect_n <= 1'b1;
cfg_err_posted_n <= 1'b0;
cfg_interrupt_n <= 1'b1;
cfg_turnoff_ok_n <= 1'b1;
cfg_dwaddr <= 0;
cfg_err_tlp_cpl_header <= 0;
cfg_di <= 0;
cfg_byte_en_n <= 4'hf;
cfg_wr_en_n <= 1;
cfg_rd_en_n <= 1;
cfg_pm_wake_n <= 1;
cfg_trn_pending_n <= 1'b0;
end
/************************************************************
Task : TSK_READ_CFG_DW
Description : Read Configuration Space DW
*************************************************************/
task TSK_READ_CFG_DW;
input [31:0] addr_;
begin
if (!trn_reset_n) begin
$display("[%t] : trn_reset_n is asserted", $realtime);
$finish(1);
end
wait ( cfg_rd_wr_done_n == 1'b1)
@(posedge trn_clk);
cfg_dwaddr <= #(Tcq) addr_;
cfg_wr_en_n <= #(Tcq) 1'b1;
cfg_rd_en_n <= #(Tcq) 1'b0;
$display("[%t] : Reading Cfg Addr [0x%h]", $realtime, addr_);
$fdisplay(board.RP.com_usrapp.tx_file_ptr,
"\n[%t] : Local Configuration Read Access :",
$realtime);
@(posedge trn_clk);
#(Tcq);
wait ( cfg_rd_wr_done_n == 1'b0)
#(Tcq);
$fdisplay(board.RP.com_usrapp.tx_file_ptr,
"\t\t\tCfg Addr [0x%h] -> Data [0x%h]\n",
{addr_,2'b00}, cfg_do);
cfg_rd_en_n <= #(Tcq) 1'b1;
end
endtask // TSK_READ_CFG_DW;
/************************************************************
Task : TSK_WRITE_CFG_DW
Description : Write Configuration Space DW
*************************************************************/
task TSK_WRITE_CFG_DW;
input [31:0] addr_;
input [31:0] data_;
input [3:0] ben_;
begin
if (!trn_reset_n) begin
$display("[%t] : trn_reset_n is asserted", $realtime);
$finish(1);
end
wait ( cfg_rd_wr_done_n == 1'b1)
@(posedge trn_clk);
cfg_dwaddr <= #(Tcq) addr_;
cfg_di <= #(Tcq) data_;
cfg_byte_en_n <= #(Tcq) ben_;
cfg_wr_en_n <= #(Tcq) 1'b0;
cfg_rd_en_n <= #(Tcq) 1'b1;
$display("[%t] : Writing Cfg Addr [0x%h]", $realtime, addr_);
$fdisplay(board.RP.com_usrapp.tx_file_ptr,
"\n[%t] : Local Configuration Write Access :",
$realtime);
@(posedge trn_clk);
#(Tcq);
wait ( cfg_rd_wr_done_n == 1'b0)
#(Tcq);
cfg_wr_en_n <= #(Tcq) 1'b1;
end
endtask // TSK_WRITE_CFG_DW;
endmodule // pci_exp_usrapp_cfg
hdl/sim/pcie/pci_exp_usrapp_com.v 0 → 100644
View file @ be11df22
This diff is collapsed.
hdl/sim/pcie/pci_exp_usrapp_pl.v 0 → 100644
View file @ be11df22
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pci_exp_usrapp_pl.v
// Version : 1.8
//--
//--------------------------------------------------------------------------------
module pci_exp_usrapp_pl (
pl_initial_link_width,
pl_lane_reversal_mode,
pl_link_gen2_capable,
pl_link_partner_gen2_supported,
pl_link_upcfg_capable,
pl_ltssm_state,
pl_received_hot_rst,
pl_sel_link_rate,
pl_sel_link_width,
pl_directed_link_auton,
pl_directed_link_change,
pl_directed_link_speed,
pl_directed_link_width,
pl_upstream_prefer_deemph,
speed_change_done_n,
trn_lnk_up_n,
trn_clk,
trn_reset_n
);
input [2:0] pl_initial_link_width;
input [1:0] pl_lane_reversal_mode;
input pl_link_gen2_capable;
input pl_link_partner_gen2_supported;
input pl_link_upcfg_capable;
input [5:0] pl_ltssm_state;
input pl_received_hot_rst;
input pl_sel_link_rate;
input [1:0] pl_sel_link_width;
output pl_directed_link_auton;
output [1:0] pl_directed_link_change;
output pl_directed_link_speed;
output [1:0] pl_directed_link_width;
output pl_upstream_prefer_deemph;
output speed_change_done_n;
input trn_lnk_up_n;
input trn_clk;
input trn_reset_n;
parameter Tcq = 1;
parameter LINK_CAP_MAX_LINK_SPEED = 4'h1;
reg pl_directed_link_auton;
reg [1:0] pl_directed_link_change;
reg pl_directed_link_speed;
reg [1:0] pl_directed_link_width;
reg pl_upstream_prefer_deemph;
reg speed_change_done_n;
initial begin
pl_directed_link_auton <= 1'b0;
pl_directed_link_change <= 2'b0;
pl_directed_link_speed <= 1'b0;
pl_directed_link_width <= 2'b0;
pl_upstream_prefer_deemph <= 1'b0;
speed_change_done_n <= 1'b1;
if (LINK_CAP_MAX_LINK_SPEED == 4'h2) begin
wait (trn_lnk_up_n == 1'b0);
if (pl_link_gen2_capable && pl_link_partner_gen2_supported) begin
wait (pl_sel_link_rate == 1'h1);
wait (pl_ltssm_state == 6'h16);
speed_change_done_n <= 1'b0;
end
end
end
endmodule // pci_exp_usrapp_pl
hdl/sim/pcie/pci_exp_usrapp_rx.v 0 → 100644
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hdl/sim/pcie/pcie_axi_trn_bridge.v 0 → 100644
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//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : sys_clk_gen.v
// Version : 1.7
//--
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module sys_clk_gen (sys_clk);
output sys_clk;
reg sys_clk;
parameter offset = 0;
parameter halfcycle = 500;
initial begin
sys_clk = 0;
#(offset);
forever #(halfcycle) sys_clk = ~sys_clk;
end
endmodule // sys_clk_gen
hdl/sim/pcie/sys_clk_gen_ds.v 0 → 100644
View file @ be11df22
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : sys_clk_gen_ds.v
// Version : 1.7
//--
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module sys_clk_gen_ds (sys_clk_p, sys_clk_n);
output sys_clk_p;
output sys_clk_n;
parameter offset = 0;
parameter halfcycle = 500;
sys_clk_gen #(
.offset( offset ),
.halfcycle( halfcycle )
)
clk_gen (
.sys_clk(sys_clk_p)
);
assign sys_clk_n = !sys_clk_p;
endmodule // sys_clk_gen_ds
hdl/sim/pcie/tests.v 0 → 100644
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`include "sample_tests1.v"
`include "tf64_pcie_axi.v"
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hdl/testbench/pcie/Manifest.py
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import os as __os
import shutil as __shutil
def __import_verilog_lib():
xilinx_dir = __os.getenv("XILINX");
if xilinx_dir == None:
print("XILINX variable not set")
__os.exit(-1)
if __os.path.isdir("work"):
return
verilog_lib = xilinx_dir + "/ISE/verilog/src/glbl.v"
print("Copying " + verilog_lib)
#__os.mkdir("work")
__shutil.copy(verilog_lib, ".")
target = "xilinx"
action = "simulation"
vlog_opt = "-i ../../sim/pcie -d SIMULATION"
# ENABLE_GT has to be set until I figure out a way
# to force ISIM to work in PIPE simulation mode
vlog_opt += " -d ENABLE_GT"
vsim_opt = "-testplusarg TESTNAME=tf64_pcie_axi"
__import_verilog_lib()
files = ["board.v",
"glbl.v"]
syn_project = "bpm_pcie_sim.xise"
#top_module = "tf64_pcie_axi"
modules = {"local" : ["../../modules/pcie",
"../../ip_cores/pcie/7k325ffg900"]}
"../../ip_cores/pcie/7k325ffg900",
"../../sim/pcie",
"../../top/pcie"]}
files = "tf64_pcie_axi.v"
hdl/testbench/pcie/Test01.wcfg
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hdl/testbench/pcie/board.f 0 → 100644
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../../ip_cores/pcie/7k325ffg900/bram_x64.vhd
../../ip_cores/pcie/7k325ffg900/eb_fifo_counted_resized.vhd
../../ip_cores/pcie/7k325ffg900/mbuf_128x72.vhd
../../ip_cores/pcie/7k325ffg900/prime_FIFO_plain.vhd
../../ip_cores/pcie/7k325ffg900/sfifo_15x128.vhd
../../modules/pcie/common/v6abb64Package_efifo_elink.vhd
../../modules/pcie/common/DDR_Blinker.vhd
../../modules/pcie/common/DMA_Calculate.vhd
../../modules/pcie/common/DMA_FSM.vhd
../../modules/pcie/common/FF_tagram64x36.vhd
../../modules/pcie/common/FIFO_Wrapper.vhd
../../modules/pcie/common/FIFO_Wrapper_Loopback.vhd
../../modules/pcie/common/Interrupts.vhd
../../modules/pcie/common/PCIe_UserLogic_00.vhd
../../modules/pcie/common/Registers.vhd
../../modules/pcie/common/RxIn_Delays.vhd
../../modules/pcie/common/Tx_Output_Arbitor.vhd
../../modules/pcie/common/bram_DDRs_Control.vhd
../../modules/pcie/common/bram_DDRs_Control_Loopback.vhd
../../modules/pcie/common/rx_CplD_Channel.vhd
../../modules/pcie/common/rx_MRd_Channel.vhd
../../modules/pcie/common/rx_MWr_Channel.vhd
../../modules/pcie/common/rx_Transact.vhd
../../modules/pcie/common/rx_dsDMA_Channel.vhd
../../modules/pcie/common/rx_usDMA_Channel.vhd
../../modules/pcie/common/tlpControl.vhd
../../modules/pcie/common/tx_Mem_Reader.vhd
../../modules/pcie/common/tx_Transact.vhd
../../top/pcie/bpm_pcie_k7.vhd
hdl/testbench/pcie/board.v 0 → 100644
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hdl/testbench/pcie/board_vlog.f 0 → 100644
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board.v
../../sim/pcie/sys_clk_gen.v
../../sim/pcie/sys_clk_gen_ds.v
../../sim/pcie/xilinx_pcie_2_1_rport_7x.v
../../sim/pcie/pcie_2_1_rport_7x.v
../../sim/pcie/pcie_axi_trn_bridge.v
../../sim/pcie/pci_exp_usrapp_com.v
../../sim/pcie/pci_exp_usrapp_tx.v
../../sim/pcie/pci_exp_usrapp_cfg.v
../../sim/pcie/pci_exp_usrapp_rx.v
../../sim/pcie/pci_exp_usrapp_pl.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_wrapper.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gtp_pipe_rate.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gtp_pipe_reset.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_qpll_wrapper.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_qpll_drp.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_qpll_reset.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_rxeq_scan.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_eq.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_clock.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_drp.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_rate.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_reset.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_user.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_sync.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_wrapper.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_rx_valid_filter_7x.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_top.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_top_pipe_mode.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_bram_top_7x.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_brams_7x.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_bram_7x.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_7x.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_pipe_pipeline.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_pipe_lane.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_pipe_misc.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_tx_thrtl_ctl.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_rx.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_rx_null_gen.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_rx_pipeline.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_tx_pipeline.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_tx.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_top.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_top.v
../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core.v
hdl/testbench/pcie/isim_cmd.tcl 0 → 100644
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# ISIM Commands
run all
quit
hdl/testbench/pcie/pipe_interconnect.v 0 → 100644
View file @ be11df22
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pipe_interconnect.v
// Version : 1.7
`define EP board.EP.pcie_core_i.pcie_top_i
`define RP board.RP.rport.pcie_top_i
//---------------------------------------------------------- PIO RTL & RP simulation -------------------------------------------------------------------//
generate
if (PIPE_SIM == "TRUE")
begin
assign `EP.pipe_rx0_char_is_k_gt = `RP.pipe_tx0_char_is_k_gt;
assign `EP.pipe_rx1_char_is_k_gt = `RP.pipe_tx1_char_is_k_gt;
assign `EP.pipe_rx2_char_is_k_gt = `RP.pipe_tx2_char_is_k_gt;
assign `EP.pipe_rx3_char_is_k_gt = `RP.pipe_tx3_char_is_k_gt;
assign `EP.pipe_rx4_char_is_k_gt = `RP.pipe_tx4_char_is_k_gt;
assign `EP.pipe_rx5_char_is_k_gt = `RP.pipe_tx5_char_is_k_gt;
assign `EP.pipe_rx6_char_is_k_gt = `RP.pipe_tx6_char_is_k_gt;
assign `EP.pipe_rx7_char_is_k_gt = `RP.pipe_tx7_char_is_k_gt;
assign `EP.pipe_rx0_data_gt = `RP.pipe_tx0_data_gt;
assign `EP.pipe_rx1_data_gt = `RP.pipe_tx1_data_gt;
assign `EP.pipe_rx2_data_gt = `RP.pipe_tx2_data_gt;
assign `EP.pipe_rx3_data_gt = `RP.pipe_tx3_data_gt;
assign `EP.pipe_rx4_data_gt = `RP.pipe_tx4_data_gt;
assign `EP.pipe_rx5_data_gt = `RP.pipe_tx5_data_gt;
assign `EP.pipe_rx6_data_gt = `RP.pipe_tx6_data_gt;
assign `EP.pipe_rx7_data_gt = `RP.pipe_tx7_data_gt;
//-------------------------------------------------------------------------------------------------------------------------//
assign `RP.pipe_rx0_char_is_k_gt = `EP.pipe_tx0_char_is_k_gt;
assign `RP.pipe_rx1_char_is_k_gt = `EP.pipe_tx1_char_is_k_gt;
assign `RP.pipe_rx2_char_is_k_gt = `EP.pipe_tx2_char_is_k_gt;
assign `RP.pipe_rx3_char_is_k_gt = `EP.pipe_tx3_char_is_k_gt;
assign `RP.pipe_rx4_char_is_k_gt = `EP.pipe_tx4_char_is_k_gt;
assign `RP.pipe_rx5_char_is_k_gt = `EP.pipe_tx5_char_is_k_gt;
assign `RP.pipe_rx6_char_is_k_gt = `EP.pipe_tx6_char_is_k_gt;
assign `RP.pipe_rx7_char_is_k_gt = `EP.pipe_tx7_char_is_k_gt;
assign `RP.pipe_rx0_data_gt = `EP.pipe_tx0_data_gt;
assign `RP.pipe_rx1_data_gt = `EP.pipe_tx1_data_gt;
assign `RP.pipe_rx2_data_gt = `EP.pipe_tx2_data_gt;
assign `RP.pipe_rx3_data_gt = `EP.pipe_tx3_data_gt;
assign `RP.pipe_rx4_data_gt = `EP.pipe_tx4_data_gt;
assign `RP.pipe_rx5_data_gt = `EP.pipe_tx5_data_gt;
assign `RP.pipe_rx6_data_gt = `EP.pipe_tx6_data_gt;
assign `RP.pipe_rx7_data_gt = `EP.pipe_tx7_data_gt;
end
endgenerate
//----------------------------------------------------------------------------------------------------------------------------------------------------------//
hdl/testbench/pcie/simulate_isim.sh 0 → 100755
View file @ be11df22
#!/bin/sh
#TEST=sample_smoke_test0
TEST=tf64_pcie_axi
# compile all of the files
# Include -d ENABLE_GT to run the simulations in GT mode
vlogcomp -work work -d ENABLE_GT -d SIMULATION -i . -i ../../sim/pcie --incremental -f board_vlog.f && \
vhpcomp -work work --incremental -f board.f && \
vlogcomp -work work $XILINX/verilog/src/glbl.v && \
# compile and link source files
fuse work.board work.glbl -d ENABLE_GT -d SIMULATION -L unisims_ver -L unimacro_ver -L unisim -L unimacro -L secureip -o tb_sim
# set BATCH_MODE=0 to run simulation in GUI mode
BATCH_MODE=0
if [ $BATCH_MODE == 1 ]; then
# run the simulation in batch mode
./tb_sim -wdb wave_isim -tclbatch isim_cmd.tcl -testplusarg TESTNAME=$TEST
else
# run the simulation in gui mode
./tb_sim -gui -view Test01.wcfg -wdb wave_isim -tclbatch isim_cmd.tcl -testplusarg TESTNAME=$TEST
fi
hdl/testbench/pcie/tf64_pcie_axi.v
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hdl/top/pcie/bpm_pcie_k7.vhd
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