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Commit e83be099 authored by Adrian Byszuk's avatar Adrian Byszuk
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Update PCIe core to v1.8, add PIPE simulation mode

parent 230d9e1e
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hdl/ip_cores/pcie/7k325ffg900/coregen.cgc
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hdl/ip_cores/pcie/7k325ffg900/coregen.cgp
View file @ e83be099
# Date: Tue Dec 18 14:10:58 2012
# Date: Mon Jan 7 12:25:40 2013
SET addpads = false
SET asysymbol = false
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core.xco
View file @ e83be099
##############################################################
#
# Xilinx Core Generator version 14.3
# Date: Tue Dec 18 14:08:16 2012
# Xilinx Core Generator version 14.4
# Date: Mon Jan 7 12:20:59 2013
#
##############################################################
#
......@@ -12,7 +12,7 @@
#
##############################################################
#
# Generated from component: xilinx.com:ip:pcie_7x:1.7
# Generated from component: xilinx.com:ip:pcie_7x:1.8
#
##############################################################
#
......@@ -36,7 +36,7 @@ SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT 7_Series_Integrated_Block_for_PCI_Express xilinx.com:ip:pcie_7x:1.7
SELECT 7_Series_Integrated_Block_for_PCI_Express xilinx.com:ip:pcie_7x:1.8
# END Select
# BEGIN Parameters
CSET acceptable_l0s_latency=Maximum_of_64_ns
......@@ -209,7 +209,7 @@ CSET pcie_debug_ports=false
CSET pcie_fast_config=None
CSET perf_level=High
CSET phantom_functions=No_function_number_bits_used
CSET pipe_sim=false
CSET pipe_sim=true
CSET prefetchable_memory_base_limit_registers=Disabled
CSET rbar_enabled=false
CSET rbar_initial_value0=0
......@@ -222,13 +222,13 @@ CSET rbar_num=0
CSET rcb=64_byte
CSET receive_np_request=true
CSET recrc_check=0
CSET recrc_check_trim=false
CSET recrc_check_trim=true
CSET ref_clk_freq=100_MHz
CSET replay_timeout_func=Add
CSET replay_timeout_value=0000
CSET revision_id=00
CSET root_cap_crs=false
CSET silicon_rev=General_ES
CSET silicon_rev=GES_and_Production
CSET slot_cap_attn_butn=false
CSET slot_cap_attn_ind=false
CSET slot_cap_elec_interlock=false
......@@ -260,7 +260,7 @@ CSET vsec_enabled=false
CSET xlnx_ref_board=None
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-09-21T16:21:42Z
MISC pkg_timestamp=2012-11-30T13:01:13Z
# END Extra information
GENERATE
# CRC: ecf273fe
# CRC: 26bb8af
hdl/ip_cores/pcie/7k325ffg900/pcie_core.xise
View file @ e83be099
......@@ -12,7 +12,7 @@
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.3" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
<files/>
......@@ -326,8 +326,8 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-12-18T15:08:29" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="95459FCE785220BC1F152FA2572CF68A" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-01-07T13:21:07" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="E149697567196E1B2F7C4ACF0D513DAC" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_rx.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_axi_basic_rx.v
// Version : 1.7
// Version : 1.8
// //
// Description: //
// TRN to AXI RX module. Instantiates pipeline and null generator RX //
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_rx_null_gen.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_axi_basic_rx_null_gen.v
// Version : 1.7
// Version : 1.8
// //
// Description: //
// TRN to AXI RX null generator. Generates null packets for use in //
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_rx_pipeline.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_axi_basic_rx_pipeline.v
// Version : 1.7
// Version : 1.8
// //
// Description: //
// TRN to AXI RX pipeline. Converts received data from TRN protocol to AXI. //
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_top.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_axi_basic_top.v
// Version : 1.7
// Version : 1.8
// //
// Description: //
// TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules. //
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_tx.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_axi_basic_tx.v
// Version : 1.7
// Version : 1.8
// //
// Description: //
// AXI to TRN TX module. Instantiates pipeline and throttle control TX //
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_tx_pipeline.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_axi_basic_tx_pipeline.v
// Version : 1.7
// Version : 1.8
// //
// Description: //
// AXI to TRN TX pipeline. Converts transmitted data from AXI protocol to //
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_tx_thrtl_ctl.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_axi_basic_tx_thrtl_ctl.v
// Version : 1.7
// Version : 1.8
// //
// Description: //
// TX throttle controller. Anticipates back-pressure from PCIe block and //
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_rx_valid_filter_7x.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_gt_rx_valid_filter_7x.v
// Version : 1.7
// Version : 1.8
//-- Description: GTX module for 7-series Integrated PCIe Block
//--
//--
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_top.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_gt_top.v
// Version : 1.7
// Version : 1.8
//-- Description: GTX module for 7-series Integrated PCIe Block
//--
//--
......@@ -251,7 +251,8 @@ module pcie_core_gt_top #
localparam PCIE_LINK_SPEED = (PL_FAST_TRAIN == "TRUE") ? 2 : 3;
// The parameter PCIE_OOBCLK_MODE_ENABLE value should be "0" for simulation and for synthesis it should be 1
localparam PCIE_OOBCLK_MODE_ENABLE = (PL_FAST_TRAIN == "TRUE") ? 0 : 1;
//localparam PCIE_OOBCLK_MODE_ENABLE = (PL_FAST_TRAIN == "TRUE") ? 0 : 1;
localparam PCIE_OOBCLK_MODE_ENABLE = 1;
localparam PCIE_TX_EIDLE_ASSERT_DELAY = (PL_FAST_TRAIN == "TRUE") ? 4 : 2;
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gtp_pipe_rate.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_gtp_pipe_rate.v
// Version : 1.7
// Version : 1.8
//------------------------------------------------------------------------------
// Filename : gtp_pipe_rate.v
// Description : PIPE Rate Module for 7 Series Transceiver
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gtp_pipe_reset.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_gtp_pipe_reset.v
// Version : 1.7
// Version : 1.8
//------------------------------------------------------------------------------
// Filename : gtp_pipe_reset.v
// Description : GTP PIPE Reset Module for 7 Series Transceiver
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_7x.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_pcie_7x.v
// Version : 1.7
// Version : 1.8
//
// Description: Solution wrapper for Virtex7 Hard Block for PCI Express
//
......@@ -446,6 +446,7 @@ module pcie_core_pcie_7x # (
input wire user_clk2,
input wire user_clk_prebuf,
input wire user_clk_prebuf_en,
`ifdef B_TESTMODE
input wire scanmode_n,
input wire scanenable_n,
input wire edt_clk,
......@@ -464,6 +465,7 @@ module pcie_core_pcie_7x # (
input wire pmv_enable_n,
input wire [2:0] pmv_select,
input wire [1:0] pmv_divide,
`endif
input wire sys_rst_n,
input wire cm_rst_n,
input wire cm_sticky_rst_n,
......@@ -472,10 +474,10 @@ module pcie_core_pcie_7x # (
input wire dl_rst_n,
input wire pl_rst_n,
input wire pl_transmit_hot_rst,
input wire cfg_reset,
input wire gwe,
input wire grestore,
input wire ghigh,
// input wire cfg_reset,
// input wire gwe,
// input wire grestore,
// input wire ghigh,
input wire [31:0] cfg_mgmt_di,
input wire [3:0] cfg_mgmt_byte_en_n,
input wire [9:0] cfg_mgmt_dwaddr,
......@@ -653,7 +655,9 @@ module pcie_core_pcie_7x # (
output wire [1:0] pipe_tx5_powerdown,
output wire [1:0] pipe_tx6_powerdown,
output wire [1:0] pipe_tx7_powerdown,
`ifdef B_TESTMODE
output wire pmv_out,
`endif
output wire user_rst_n,
output wire pl_received_hot_rst,
output wire received_func_lvl_rst_n,
......@@ -774,8 +778,8 @@ module pcie_core_pcie_7x # (
output wire dbg_sclr_i,
output wire dbg_sclr_j,
output wire dbg_sclr_k,
output wire [11:0] pl_dbg_vec,
output wire [18:0] xil_unconn_out
output wire [11:0] pl_dbg_vec
// output wire [18:0] xil_unconn_out
);
localparam TCQ = 1;
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_bram_7x.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_pcie_bram_7x.v
// Version : 1.7
// Version : 1.8
// Description : single bram wrapper for the mb pcie block
// The bram A port is the write port
// the B port is the read port
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_bram_top_7x.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_pcie_bram_top_7x.v
// Version : 1.7
// Version : 1.8
// Description : bram wrapper for Tx and Rx
// given the pcie block attributes calculate the number of brams
// and pipeline stages and instantiate the brams
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_brams_7x.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_pcie_brams_7x.v
// Version : 1.7
// Version : 1.8
// Description : pcie bram wrapper
// arrange and connect brams
// implement address decoding, datapath muxing and pipeline stages
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_pipe_lane.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_pcie_pipe_lane.v
// Version : 1.7
// Version : 1.8
//
// Description: PIPE per lane module for 7-Series PCIe Block
//
......@@ -102,36 +102,6 @@ module pcie_core_pcie_pipe_lane #
parameter TCQ = 1; // clock to out delay model
reg [ 1:0] pipe_rx_char_is_k_q ;
reg [15:0] pipe_rx_data_q ;
reg pipe_rx_valid_q ;
reg pipe_rx_chanisaligned_q ;
reg [ 2:0] pipe_rx_status_q ;
reg pipe_rx_phy_status_q ;
reg pipe_rx_elec_idle_q ;
reg pipe_rx_polarity_q ;
reg pipe_tx_compliance_q ;
reg [ 1:0] pipe_tx_char_is_k_q ;
reg [15:0] pipe_tx_data_q ;
reg pipe_tx_elec_idle_q ;
reg [ 1:0] pipe_tx_powerdown_q ;
reg [ 1:0] pipe_rx_char_is_k_qq ;
reg [15:0] pipe_rx_data_qq ;
reg pipe_rx_valid_qq ;
reg pipe_rx_chanisaligned_qq;
reg [ 2:0] pipe_rx_status_qq ;
reg pipe_rx_phy_status_qq ;
reg pipe_rx_elec_idle_qq ;
reg pipe_rx_polarity_qq ;
reg pipe_tx_compliance_qq ;
reg [ 1:0] pipe_tx_char_is_k_qq ;
reg [15:0] pipe_tx_data_qq ;
reg pipe_tx_elec_idle_qq ;
reg [ 1:0] pipe_tx_powerdown_qq ;
generate
if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0
......@@ -154,6 +124,21 @@ module pcie_core_pcie_pipe_lane #
end // if (PIPE_PIPELINE_STAGES == 0)
else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1
reg [ 1:0] pipe_rx_char_is_k_q ;
reg [15:0] pipe_rx_data_q ;
reg pipe_rx_valid_q ;
reg pipe_rx_chanisaligned_q ;
reg [ 2:0] pipe_rx_status_q ;
reg pipe_rx_phy_status_q ;
reg pipe_rx_elec_idle_q ;
reg pipe_rx_polarity_q ;
reg pipe_tx_compliance_q ;
reg [ 1:0] pipe_tx_char_is_k_q ;
reg [15:0] pipe_tx_data_q ;
reg pipe_tx_elec_idle_q ;
reg [ 1:0] pipe_tx_powerdown_q ;
always @(posedge pipe_clk) begin
if (rst_n)
......@@ -215,6 +200,36 @@ module pcie_core_pcie_pipe_lane #
end // if (PIPE_PIPELINE_STAGES == 1)
else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2
reg [ 1:0] pipe_rx_char_is_k_q ;
reg [15:0] pipe_rx_data_q ;
reg pipe_rx_valid_q ;
reg pipe_rx_chanisaligned_q ;
reg [ 2:0] pipe_rx_status_q ;
reg pipe_rx_phy_status_q ;
reg pipe_rx_elec_idle_q ;
reg pipe_rx_polarity_q ;
reg pipe_tx_compliance_q ;
reg [ 1:0] pipe_tx_char_is_k_q ;
reg [15:0] pipe_tx_data_q ;
reg pipe_tx_elec_idle_q ;
reg [ 1:0] pipe_tx_powerdown_q ;
reg [ 1:0] pipe_rx_char_is_k_qq ;
reg [15:0] pipe_rx_data_qq ;
reg pipe_rx_valid_qq ;
reg pipe_rx_chanisaligned_qq;
reg [ 2:0] pipe_rx_status_qq ;
reg pipe_rx_phy_status_qq ;
reg pipe_rx_elec_idle_qq ;
reg pipe_rx_polarity_qq ;
reg pipe_tx_compliance_qq ;
reg [ 1:0] pipe_tx_char_is_k_qq ;
reg [15:0] pipe_tx_data_qq ;
reg pipe_tx_elec_idle_qq ;
reg [ 1:0] pipe_tx_powerdown_qq ;
always @(posedge pipe_clk) begin
if (rst_n)
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_pipe_misc.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_pcie_pipe_misc.v
// Version : 1.7
// Version : 1.8
//
// Description: Misc PIPE module for 7-Series PCIe Block
//
......@@ -89,20 +89,6 @@ module pcie_core_pcie_pipe_misc #
parameter TCQ = 1; // clock to out delay model
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
reg pipe_tx_rcvr_det_qq ;
reg pipe_tx_reset_qq ;
reg pipe_tx_rate_qq ;
reg pipe_tx_deemph_qq ;
reg [2:0] pipe_tx_margin_qq ;
reg pipe_tx_swing_qq ;
generate
if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0
......@@ -117,6 +103,13 @@ module pcie_core_pcie_pipe_misc #
end // if (PIPE_PIPELINE_STAGES == 0)
else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
always @(posedge pipe_clk) begin
if (rst_n)
......@@ -154,6 +147,20 @@ module pcie_core_pcie_pipe_misc #
end // if (PIPE_PIPELINE_STAGES == 1)
else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
reg pipe_tx_rcvr_det_qq ;
reg pipe_tx_reset_qq ;
reg pipe_tx_rate_qq ;
reg pipe_tx_deemph_qq ;
reg [2:0] pipe_tx_margin_qq ;
reg pipe_tx_swing_qq ;
always @(posedge pipe_clk) begin
if (rst_n)
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_pipe_pipeline.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_pcie_pipe_pipeline.v
// Version : 1.7
// Version : 1.8
//
// Description: PIPE module for Virtex7 PCIe Block
//
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_top.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_pcie_top.v
// Version : 1.7
// Version : 1.8
// Description: Solution wrapper for Virtex7 Hard Block for PCI Express
//
//
......@@ -1059,7 +1059,7 @@ pcie_core_axi_basic_top #(
.trn_rsrc_dsc (trn_rsrc_dsc), // input
.trn_rrem (trn_rrem), // input
.trn_rerrfwd (trn_rerrfwd), // input
.trn_rbar_hit (trn_rbar_hit), // input
.trn_rbar_hit (trn_rbar_hit[6:0]), // input
.trn_recrc_err (trn_recrc_err), // input
// TRN Misc.
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_clock.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_pipe_clock.v
// Version : 1.7
// Version : 1.8
//------------------------------------------------------------------------------
// Filename : pipe_clock.v
// Description : PIPE Clock Module for 7 Series Transceiver
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_eq.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_pipe_eq.v
// Version : 1.7
// Version : 1.8
//------------------------------------------------------------------------------
// Filename : pipe_eq.v
// Description : PIPE Equalization Module for 7 Series Transceiver
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_rate.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_pipe_rate.v
// Version : 1.7
// Version : 1.8
//------------------------------------------------------------------------------
// Filename : pipe_rate.v
// Description : PIPE Rate Module for 7 Series Transceiver
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_reset.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_pipe_reset.v
// Version : 1.7
// Version : 1.8
//------------------------------------------------------------------------------
// Filename : pipe_reset.v
// Description : PIPE Reset Module for 7 Series Transceiver
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_sync.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_pipe_sync.v
// Version : 1.7
// Version : 1.8
//------------------------------------------------------------------------------
// Filename : pipe_sync.v
// Description : PIPE Sync Module for 7 Series Transceiver
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_user.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_pipe_user.v
// Version : 1.7
// Version : 1.8
//------------------------------------------------------------------------------
// Filename : pipe_user.v
// Description : PIPE User Module for 7 Series Transceiver
......@@ -178,7 +178,7 @@ module pcie_core_pipe_user #
localparam FSM_RESET = 2'd3;
//---------- Simulation Speedup ------------------------
localparam converge_max_cnt = PCIE_SIM_MODE ? 22'd100 : CONVERGE_MAX;
localparam converge_max_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd100 : CONVERGE_MAX;
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_wrapper.v
View file @ e83be099
......@@ -49,11 +49,11 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_pipe_wrapper.v
// Version : 1.7
// Version : 1.8
//------------------------------------------------------------------------------
// Filename : pipe_wrapper.v
// Description : PIPE Wrapper for 7 Series Transceiver
// Version : 18.0
// Version : 18.1
//------------------------------------------------------------------------------
//---------- PIPE Wrapper Hierarchy --------------------------------------------
......@@ -85,8 +85,8 @@
// : "GTP"
// PCIE_USE_MODE : "1.0" = GTX IES 325T or GTP IES use mode.
// : "1.1" = GTX IES 485T use mode.
// : "2.0" = GTH IES 690T use mode.
// : "2.1" = GTH GES 690T use mode for 1.2 silicon.
// : "2.0" = GTH IES 690T use mode for 1.0 silicon.
// : "2.1" = GTH GES 690T use mode for 1.2 silicon. SW model use "2.0"
// : "3.0" = GTX GES 325T or 485T use mode (default).
// PCIE_PLL_SEL : "CPLL" (default)
// : "QPLL"
......@@ -252,6 +252,7 @@ module pcie_core_pipe_wrapper #
output [(PCIE_LANE*3)-1:0] PIPE_RXBUFSTATUS, // PCLK | RXUSRCLK
//---------- PIPE User Ports ---------------------------
//input PIPE_MMCM_RST_N, // Async | Async
input [PCIE_LANE-1:0] PIPE_RXSLIDE, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_CPLL_LOCK, // Async | Async
......@@ -593,7 +594,8 @@ generate
.CLK_CLK (PIPE_CLK),
.CLK_TXOUTCLK (gt_txoutclk[0]), // Reference clock from lane 0
.CLK_RXOUTCLK_IN (gt_rxoutclk),
.CLK_RST_N (1'b1),
.CLK_RST_N (1'b1),
//.CLK_RST_N (PIPE_MMCM_RST_N), // Allow system reset for error recovery
.CLK_PCLK_SEL (rate_pclk_sel),
.CLK_GEN3 (rate_gen3[0]),
......@@ -1107,8 +1109,10 @@ generate for (i=0; i<PCIE_LANE; i=i+1)
pcie_core_pipe_drp #
(
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_RXBUF_EN (PCIE_RXBUF_EN), // PCIe RX buffer enable for Gen3 only
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_qpll_drp.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_qpll_drp.v
// Version : 1.7
// Version : 1.8
//------------------------------------------------------------------------------
// Filename : qpll_drp.v
// Description : QPLL DRP Module for 7 Series Transceiver
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_qpll_reset.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_qpll_reset.v
// Version : 1.7
// Version : 1.8
//------------------------------------------------------------------------------
// Filename : qpll_reset.v
// Description : QPLL Reset Module for 7 Series Transceiver
......
hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_rxeq_scan.v
View file @ e83be099
......@@ -49,7 +49,7 @@
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_rxeq_scan.v
// Version : 1.7
// Version : 1.8
//------------------------------------------------------------------------------
// Filename : rxeq_scan.v
// Description : PIPE RX Equalization Eye Scan Module for 7 Series Transceiver
......@@ -67,7 +67,8 @@ module pcie_core_rxeq_scan #
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_RXEQ_MODE_GEN3 = 1, // PCIe RX equalization mode
parameter CONVERGE_MAX = 22'd3125000 // Convergence max count
parameter CONVERGE_MAX = 22'd3125000, // Convergence max count (12ms)
parameter CONVERGE_MAX_BYPASS = 22'd2083333 // Convergence max count for phase2/3 bypass mode (8ms)
)
(
......@@ -134,7 +135,8 @@ module pcie_core_rxeq_scan #
// Gen3: 32 bits / PCLK : 1 million bits / X PCLK
// X =
//------------------------------------------------------
localparam converge_max_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd1000 : CONVERGE_MAX;
localparam converge_max_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd1000 : CONVERGE_MAX;
localparam converge_max_bypass_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd1000 : CONVERGE_MAX_BYPASS;
......@@ -281,7 +283,15 @@ begin
end
else
begin
fsm <= (converge_cnt == converge_max_cnt) ? FSM_NEW_TXCOEFF_REQ : FSM_CONVERGE;
//---------- Phase2/3 ----------------------
if (RXEQSCAN_CONTROL == 2'd2)
fsm <= (converge_cnt == converge_max_cnt) ? FSM_NEW_TXCOEFF_REQ : FSM_CONVERGE;
//---------- Phase2/3 Bypass ---------------
else
fsm <= (converge_cnt == converge_max_bypass_cnt) ? FSM_NEW_TXCOEFF_REQ : FSM_CONVERGE;
preset_done <= 1'd0;
converge_cnt <= converge_cnt + 1'd1;
new_txcoeff <= new_txcoeff;
......
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