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Beam Positoning Monitor - Gateware
Commit 2c9c53a8 authored by Adrian Byszuk's avatar Adrian Byszuk
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Update *.ucf,*.xise to v1.8 PCIe core

parent be11df22
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hdl/syn/pcie/bpm_pcie_k7.xise
View file @ 2c9c53a8
......@@ -469,73 +469,76 @@
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gtp_pipe_reset.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_rx_null_gen.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_top_pipe_mode.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_rx.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_rx_null_gen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_pipe_pipeline.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_rx.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_brams_7x.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_pipe_pipeline.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_sync.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_brams_7x.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_rxeq_scan.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_sync.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_7x.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_rxeq_scan.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_qpll_drp.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_7x.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_qpll_reset.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_qpll_drp.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_tx.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_qpll_reset.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gtp_pipe_rate.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_tx.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_top.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gtp_pipe_rate.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_eq.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_wrapper.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_eq.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_clock.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_wrapper.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_qpll_wrapper.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_clock.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_top.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_qpll_wrapper.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_rx_valid_filter_7x.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_wrapper.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_rx_valid_filter_7x.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_rate.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_wrapper.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_bram_7x.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_rate.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_bram_7x.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="14.3" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
</project>
hdl/syn/pcie/xc7k325ffg900.ucf
View file @ 2c9c53a8
......@@ -93,7 +93,7 @@ INST "refclk_ibuf" LOC = IBUFDS_GTE2_X0Y1;
# Virtex-7 GT Transceiver User Guide (UG) for more information.
#
# PCIe Lane 0
INST "pcie_core_i/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i" LOC = GTXE2_CHANNEL_X0Y7;
INST "pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i" LOC = GTXE2_CHANNEL_X0Y7;
#
# PCI Express Block placement. This constraint selects the PCI Express
......@@ -117,10 +117,10 @@ INST "pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[3].ram/
###############################################################################
NET "sys_clk_c" TNM_NET = "SYSCLK";
NET "pcie_core_i/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/clk_125mhz" TNM_NET = "CLK_125";
NET "pcie_core_i/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/clk_250mhz" TNM_NET = "CLK_250";
NET "pcie_core_i/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1" TNM_NET = "CLK_USERCLK";
NET "pcie_core_i/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk2" TNM_NET = "CLK_USERCLK2";
NET "pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/clk_125mhz" TNM_NET = "CLK_125";
NET "pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/clk_250mhz" TNM_NET = "CLK_250";
NET "pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1" TNM_NET = "CLK_USERCLK";
NET "pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk2" TNM_NET = "CLK_USERCLK2";
TIMESPEC TS_SYSCLK = PERIOD "SYSCLK" 100 MHz HIGH 50 %;
TIMESPEC TS_CLK_250 = PERIOD "CLK_250" TS_SYSCLK * 2.5 HIGH 50 % PRIORITY 1;
......@@ -130,21 +130,21 @@ TIMESPEC TS_CLK_USERCLK2 = PERIOD "CLK_USERCLK2" TS_SYSCLK / 1.6 HIGH 50 %;
INST "pcie_core_i/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i" LOC = MMCME2_ADV_X0Y2;
INST "pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i" LOC = MMCME2_ADV_X0Y2;
PIN "pcie_core_i/pcie_top_i/pcie_7x_i/pcie_block_i.PLPHYLNKUPN" TIG;
PIN "pcie_core_i/pcie_top_i/pcie_7x_i/pcie_block_i.PLRECEIVEDHOTRST" TIG;
PIN "pcie_core_i/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i.RST" TIG;
NET "pcie_core_i/gt_top_i/pipe_wrapper_i/user_resetdone*" TIG;
NET "pcie_core_i/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_sel" TIG;
NET "pcie_core_i/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_rate.pipe_rate_i/*" TNM_NET = FFS "MC_PIPE";
PIN "pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i.RST" TIG;
NET "pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/user_resetdone*" TIG;
NET "pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_sel" TIG;
NET "pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_rate.pipe_rate_i/*" TNM_NET = FFS "MC_PIPE";
TIMESPEC TS_PIPE_RATE = FROM "MC_PIPE" TS_CLK_USERCLK * 0.5;
NET "pcie_core_i/gt_top_i/pipe_wrapper_i/pipe_reset.pipe_reset_i/cpllreset" TIG;
NET "pcie_core_i/gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/clk_125mhz" TIG;
NET "pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_reset.pipe_reset_i/cpllreset" TIG;
NET "pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/clk_125mhz" TIG;
###############################################################################
# Physical Constraints
......
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