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Beam Positoning Monitor - Gateware
Commit 0ba5d79a authored by Lucas Russo's avatar Lucas Russo
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Merge branch 'trigger-rcv' into trigger-rcv-integration 

Conflicts:
	hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd
parents dd3773c0 74a1618c
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.gitignore
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*~
*.swp
*.orig
hdl/syn/*.runs*
######################
# Compilation files
######################
*Makefile
*transcript
*make_*
*_history
######################
# Modelsim
######################
*.wlf
work/
######################
# Temporary files
######################
*#*
######################
# Vivado files
######################
*.jou
*.log
*.str
*.xpr
*.edif
*.mif
.Xil/
\ No newline at end of file
hdl/modules/dbe_common/Manifest.py
View file @ 0ba5d79a
modules = { "local" : ["reset_synch",
"pulse2level"] };
"pulse2level",
"trigger_rcv",
"counter_simple",
"extend_pulse_dyn"] };
files = [ "dbe_common_pkg.vhd" ];
hdl/modules/dbe_common/counter_simple/counter_simple.vhd 0 → 100644
View file @ 0ba5d79a
-------------------------------------------------------------------------------
-- Title : Simple counter
-- Project :
-------------------------------------------------------------------------------
-- File : counter.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-11-11
-- Last update: 2015-12-11
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Simple counter for testing, with clock enable
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-11-11 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity counter_simple is
generic(
g_output_width : positive := 8
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
ce_i : in std_logic;
up_i : in std_logic;
down_i : in std_logic;
count_o : out std_logic_vector(g_output_width-1 downto 0)
);
end counter_simple;
architecture behavioural of counter_simple is
signal count : unsigned(g_output_width-1 downto 0) := to_unsigned(0, g_output_width);
begin
counter_simple : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
count <= to_unsigned(0, g_output_width);
else
if ce_i = '1' then
if up_i = '1' then
count <= count + 1;
elsif down_i = '1' then
count <= count - 1;
end if;
end if; --ce
end if; --rst
end if; -- clk
end process;
count_o <= std_logic_vector(count);
end architecture behavioural;
hdl/modules/dbe_common/dbe_common_pkg.vhd
View file @ 0ba5d79a
library ieee;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
package dbe_common_pkg is
......@@ -37,4 +38,41 @@ package dbe_common_pkg is
);
end component;
component trigger_rcv is
generic (
g_glitch_len_width : positive;
g_sync_edge : string);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
len_i : in std_logic_vector(g_glitch_len_width-1 downto 0);
data_i : in std_logic;
pulse_o : out std_logic);
end component trigger_rcv;
component extend_pulse_dyn is
generic (
g_width_bus_size : natural);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
pulse_i : in std_logic;
pulse_width_i : in unsigned(g_width_bus_size-1 downto 0);
extended_o : out std_logic := '0');
end component extend_pulse_dyn;
component counter_simple is
generic (
g_output_width : positive);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
ce_i : in std_logic;
up_i : in std_logic;
down_i : in std_logic;
count_o : out std_logic_vector(g_output_width-1 downto 0));
end component counter_simple;
end dbe_common_pkg;
hdl/modules/dbe_common/extend_pulse_dyn/extend_pulse_dyn.vhd 0 → 100644
View file @ 0ba5d79a
-------------------------------------------------------------------------------
-- Title : Dynamic pulse width extender
-- Project :
-------------------------------------------------------------------------------
-- File : extend_pulse_dyn.vhd
-- Author : Vitor Finotti Ferreira <vfinotti@finotti-Inspiron-7520>
-- Company : Brazilian Synchrotron Light Laboratory, LNLS/CNPEM
-- Created : 2016-01-22
-- Last update: 2016-01-27
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-- Synchronous pulse extender. Generates a pulse of dynamically programmable width upon
-- detection of a rising edge in the input. The code is based on
-- gc_extend_pulse.vhd created by Tomasz Wlostowskyt, from General Cores library.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Brazilian Synchrotron Light Laboratory, LNLS/CNPEM
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-dec-17 0.9 vfinotti Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
entity extend_pulse_dyn is
generic (
-- output pulse width in clk_i cycles
g_width_bus_size : natural := 32
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
pulse_i : in std_logic;
pulse_width_i : in unsigned(g_width_bus_size-1 downto 0);
-- extended output pulse
extended_o : out std_logic := '0');
end extend_pulse_dyn;
architecture rtl of extend_pulse_dyn is
signal cntr : unsigned(g_width_bus_size-1 downto 0);
signal extended_int : std_logic;
begin -- rtl
extend : process (clk_i, rst_n_i)
begin -- process extend
if rst_n_i = '0' then -- asynchronous reset (active low)
extended_int <= '0';
cntr <= (others => '0');
elsif clk_i'event and clk_i = '1' then -- rising clock edge
if(pulse_i = '1') then
extended_int <= '1';
cntr <= pulse_width_i - 2;
elsif cntr /= to_unsigned(0, cntr'length) then
cntr <= cntr - 1;
else
extended_int <= '0';
end if;
end if;
end process extend;
extended_o <= pulse_i or extended_int;
end rtl;
hdl/modules/dbe_common/trigger_rcv/trigger_rcv.vhd 0 → 100644
View file @ 0ba5d79a
-------------------------------------------------------------------------------
-- Title : Trigger receiver
-- Project :
-------------------------------------------------------------------------------
-- File : trigger_rcv.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-11-09
-- Last update: 2016-01-22
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Receives a signal from an FPGA port, debounces the signal and
-- outputs a pulse with a configurable clock width.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-11-09 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
entity trigger_rcv is
generic (
-- Number of glicth filter registers
g_glitch_len_width : positive := 8;
-- Width of the output pulse after edge detection
g_sync_edge : string := "positive"
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
len_i : in std_logic_vector(g_glitch_len_width-1 downto 0);
data_i : in std_logic;
pulse_o : out std_logic
);
end entity trigger_rcv;
architecture structural of trigger_rcv is
signal deglitched : std_logic;
signal data_sync : std_logic := '0';
component gc_dyn_glitch_filt is
generic (
g_len_width : natural);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
len_i : in std_logic_vector(g_len_width-1 downto 0);
dat_i : in std_logic;
dat_o : out std_logic);
end component gc_dyn_glitch_filt;
component gc_sync_ffs is
generic (
g_sync_edge : string);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
data_i : in std_logic;
synced_o : out std_logic;
npulse_o : out std_logic;
ppulse_o : out std_logic);
end component gc_sync_ffs;
begin
-- Prevent matastability problems
cmp_input_sync : gc_sync_ffs
generic map(
g_sync_edge => "positive")
port map(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => data_i,
synced_o => data_sync,
npulse_o => open,
ppulse_o => open);
cmp_deglitcher : gc_dyn_glitch_filt
generic map (
g_len_width => g_glitch_len_width)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
len_i => len_i,
dat_i => data_sync,
dat_o => deglitched);
cmp_edge_detector : gc_sync_ffs
generic map(
g_sync_edge => g_sync_edge)
port map(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => deglitched,
synced_o => open,
npulse_o => open,
ppulse_o => pulse_o);
end architecture structural;
hdl/modules/dbe_wishbone/Manifest.py
View file @ 0ba5d79a
......@@ -2,6 +2,9 @@ files = [ "dbe_wishbone_pkg.vhd" ];
modules = { "local" : [
"wb_stream",
"wb_trigger_iface",
"wb_trigger_mux",
"wb_trigger",
"wb_fmc150",
"wb_fmc516",
"wb_fmc130m_4ch",
......
hdl/modules/dbe_wishbone/wb_trigger/Manifest.py 0 → 100644
View file @ 0ba5d79a
files = [
"trigger_pkg.vhd",
"trigger_resolver.vhd",
"wb_trigger.vhd",
"xwb_trigger.vhd"
];
hdl/modules/dbe_wishbone/wb_trigger/trigger_pkg.vhd 0 → 100644
View file @ 0ba5d79a
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
package trigger_pkg is
-- Constants
-- Types
subtype t_trig_pulse is std_logic;
type t_trig_pulse_array is array (natural range <>) of t_trig_pulse;
type t_trig_pulse_array2d is array (natural range <>, natural range <>) of t_trig_pulse;
type t_trig_channel is record
pulse : t_trig_pulse;
end record;
type t_trig_channel_array is array (natural range <>) of t_trig_channel;
type t_trig_channel_array2d is array (natural range <>, natural range <>) of t_trig_channel;
constant c_trig_channel_dummy : t_trig_channel := (pulse => '0');
component trigger_resolver
generic (
g_trig_num : natural := 8;
g_num_mux_interfaces : natural := 2;
g_out_resolver : string := "fanout";
g_in_resolver : string := "or";
g_with_input_sync : boolean := true;
g_with_output_sync : boolean := true
);
port (
-- Reference clock for physical component (e.g., backplane, board)
ref_clk_i : in std_logic;
ref_rst_n_i : in std_logic;
-- Synchronization clocks for different domains
fs_clk_array_i : in std_logic_vector(g_num_mux_interfaces-1 downto 0);
fs_rst_n_array_i : in std_logic_vector(g_num_mux_interfaces-1 downto 0);
-------------------------------
--- Trigger ports
-------------------------------
trig_resolved_out_o : out t_trig_channel_array(g_trig_num-1 downto 0);
trig_resolved_in_i : in t_trig_channel_array(g_trig_num-1 downto 0);
trig_mux_out_o : out t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_trig_num-1 downto 0);
trig_mux_in_i : in t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_trig_num-1 downto 0)
);
end component;
end trigger_pkg;
hdl/modules/dbe_wishbone/wb_trigger/trigger_resolver.vhd 0 → 100644
View file @ 0ba5d79a
------------------------------------------------------------------------
-- Title : Wishbone Trigger Interface
-- Project :
-------------------------------------------------------------------------------
-- File : trigger_resolver.vhd
-- Author : Lucas Russo <lerwys@gmail.com>
-- Company : Brazilian Synchrotron Light Laboratory, LNLS/CNPEM
-- Created : 2016-05-11
-- Last update:
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Top module for the Wishbone Trigger MUX interface
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Brazilian Synchrotron Light Laboratory, LNLS/CNPEM
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-11 1.0 lerwys Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Common Cores
use work.gencores_pkg.all;
-- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all;
-- Reset Synch
use work.dbe_common_pkg.all;
-- Trigger types
use work.trigger_pkg.all;
entity trigger_resolver is
generic (
g_trig_num : natural := 8;
g_num_mux_interfaces : natural := 2;
g_out_resolver : string := "fanout";
g_in_resolver : string := "or";
g_with_input_sync : boolean := true;
g_with_output_sync : boolean := true
);
port (
-- Reference clock for physical component (e.g., backplane, board)
ref_clk_i : in std_logic;
ref_rst_n_i : in std_logic;
-- Synchronization clocks for different domains
fs_clk_array_i : in std_logic_vector(g_num_mux_interfaces-1 downto 0);
fs_rst_n_array_i : in std_logic_vector(g_num_mux_interfaces-1 downto 0);
-------------------------------
--- Trigger ports
-------------------------------
-- Synchronous with ref_clk
trig_resolved_out_o : out t_trig_channel_array(g_trig_num-1 downto 0);
trig_resolved_in_i : in t_trig_channel_array(g_trig_num-1 downto 0);
-- Synchronous with fs_clk_array_i(i)
trig_mux_out_o : out t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_trig_num-1 downto 0);
trig_mux_in_i : in t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_trig_num-1 downto 0)
);
end entity trigger_resolver;
architecture rtl of trigger_resolver is
signal trig_mux_out_int : t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_trig_num-1 downto 0);
signal trig_mux_out_int_synched : t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_trig_num-1 downto 0);
signal trig_mux_in_int : t_trig_channel_array(g_trig_num-1 downto 0);
-- Trigger ordered by interfaces
subtype t_trig_interface_pulses is std_logic_vector(g_num_mux_interfaces-1 downto 0);
type t_trig_interface_pulses_array is array (natural range <>) of t_trig_interface_pulses;
signal trig_mux_in_interface_pulses : t_trig_interface_pulses_array(g_trig_num-1 downto 0);
signal trig_mux_in_interface_pulses_synched : t_trig_interface_pulses_array(g_trig_num-1 downto 0);
-- From general-cores wb_crossbar module
-- If any of the bits are '1', the whole thing is '1'
-- This function makes the check explicitly have logarithmic depth.
function f_vector_OR(x : std_logic_vector)
return std_logic
is
constant len : integer := x'length;
constant mid : integer := len / 2;
alias y : std_logic_vector(len-1 downto 0) is x;
begin
if len = 1
then return y(0);
else return f_vector_OR(y(len-1 downto mid)) or
f_vector_OR(y(mid-1 downto 0));
end if;
end f_vector_OR;
begin -- architecture rtl
assert (g_out_resolver = "fanout") -- Output Resolver
report "[trigger_resolver] only g_out_resolver equal to ""fanout"" is supported!"
severity failure;
assert (g_in_resolver = "or") -- Input Resolver
report "[trigger_resolver] only g_in_resolver equal to ""or"" is supported!"
severity failure;
-----------------------------------------------------------------------------
-- Resolved triggers to Muxed triggers
-----------------------------------------------------------------------------
-- Generate Output
gen_output_interfaces : for i in 0 to g_num_mux_interfaces-1 generate
gen_output_trigger_channels : for j in 0 to g_trig_num-1 generate
gen_output_resolver_fanout : if g_out_resolver = "fanout" generate
p_output : process (ref_clk_i)
begin
if rising_edge(ref_clk_i) then
if ref_rst_n_i = '0' then
trig_mux_out_int (i, j) <= c_trig_channel_dummy;
else
trig_mux_out_int (i, j) <= trig_resolved_in_i(j);
end if;
end if;
end process;
end generate;
end generate;
end generate;
-- Resynchronize pulses to ref_clk domain
gen_sync_output_interfaces : for i in 0 to g_num_mux_interfaces-1 generate
gen_sync_output_trigger_channels : for j in 0 to g_trig_num-1 generate
gen_with_output_sync : if g_with_output_sync generate
cmp_gc_pulse_synchronizer2 : gc_pulse_synchronizer2
port map (
-- pulse input clock
clk_in_i => ref_clk_i,
rst_in_n_i => ref_rst_n_i,
-- pulse output clock
clk_out_i => fs_clk_array_i(i),
rst_out_n_i => fs_rst_n_array_i(i),
-- pulse input ready (clk_in_i domain). When HI, a pulse coming to d_p_i will be
-- correctly transferred to q_p_o.
d_ready_o => open,
-- pulse input (clk_in_i domain)
d_p_i => trig_mux_out_int(i, j).pulse,
-- pulse output (clk_out_i domain)
q_p_o => trig_mux_out_int_synched(i, j).pulse
);
end generate;
gen_without_output_sync : if not (g_with_output_sync) generate
trig_mux_out_int_synched(i, j) <= trig_mux_out_int(i, j);
end generate;
end generate;
end generate;
trig_mux_out_o <= trig_mux_out_int_synched;
-----------------------------------------------------------------------------
-- Muxed triggers to Resolved triggers
-----------------------------------------------------------------------------
-- Reorder input channels
gen_reorder_trigger_channels : for j in 0 to g_trig_num-1 generate
gen_input_interfaces : for i in 0 to g_num_mux_interfaces-1 generate
trig_mux_in_interface_pulses(j)(i) <= trig_mux_in_i(i, j).pulse;
end generate;
end generate;
-- Resynchronize pulses to ref_clk domain
gen_sync_input_trigger_channels : for j in 0 to g_trig_num-1 generate
gen_sync_input_interfaces : for i in 0 to g_num_mux_interfaces-1 generate
gen_with_input_sync : if g_with_input_sync generate
cmp_gc_pulse_synchronizer2 : gc_pulse_synchronizer2
port map (
-- pulse input clock
clk_in_i => fs_clk_array_i(i),
rst_in_n_i => fs_rst_n_array_i(i),
-- pulse output clock
clk_out_i => ref_clk_i,
rst_out_n_i => ref_rst_n_i,
-- pulse input ready (clk_in_i domain). When HI, a pulse coming to d_p_i will be
-- correctly transferred to q_p_o.
d_ready_o => open,
-- pulse input (clk_in_i domain)
d_p_i => trig_mux_in_interface_pulses(j)(i),
-- pulse output (clk_out_i domain)
q_p_o => trig_mux_in_interface_pulses_synched(j)(i)
);
end generate;
gen_without_input_sync : if not (g_with_input_sync) generate
trig_mux_in_interface_pulses_synched(j)(i) <= trig_mux_in_interface_pulses(j)(i);
end generate;
end generate;
end generate;
-- Generate Inputs (synchronous to fs_clk_array_i(j))
gen_input_trigger_channels : for j in 0 to g_trig_num-1 generate
gen_input_resolver_or : if g_in_resolver = "or" generate
p_input : process (ref_clk_i)
begin
if rising_edge(ref_clk_i) then
if ref_rst_n_i = '0' then
trig_mux_in_int(j) <= c_trig_channel_dummy;
else
trig_mux_in_int(j).pulse <= f_vector_OR(trig_mux_in_interface_pulses_synched(j));
end if;
end if;
end process;
end generate;
end generate;
trig_resolved_out_o <= trig_mux_in_int;
end architecture rtl;
hdl/modules/dbe_wishbone/wb_trigger/wb_trigger.vhd 0 → 100644
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hdl/modules/dbe_wishbone/wb_trigger/xwb_trigger.vhd 0 → 100644
View file @ 0ba5d79a
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all;
-- Trigger package
use work.trigger_pkg.all;
entity xwb_trigger is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_sync_edge : string := "positive";
g_trig_num : natural range 1 to 24 := 8; -- channels facing outside the FPGA. Limit defined by wb_trigger_regs.vhd
g_intern_num : natural range 1 to 24 := 8; -- channels facing inside the FPGA. Limit defined by wb_trigger_regs.vhd
g_rcv_intern_num : natural range 1 to 24 := 2; -- signals from inside the FPGA that can be used as input at a rcv mux.
-- Limit defined by wb_trigger_regs.vhd
g_num_mux_interfaces : natural := 2; -- Number of wb_trigger_mux modules
g_out_resolver : string := "fanout"; -- Resolver policy for output triggers
g_in_resolver : string := "or"; -- Resolver policy for input triggers
g_with_input_sync : boolean := true;
g_with_output_sync : boolean := true
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
ref_clk_i : in std_logic;
ref_rst_n_i : in std_logic;
fs_clk_array_i : in std_logic_vector(g_num_mux_interfaces-1 downto 0);
fs_rst_n_array_i : in std_logic_vector(g_num_mux_interfaces-1 downto 0);
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_trigger_iface_i : in t_wishbone_slave_in;
wb_slv_trigger_iface_o : out t_wishbone_slave_out;
wb_slv_trigger_mux_i : in t_wishbone_slave_in_array(g_num_mux_interfaces-1 downto 0);
wb_slv_trigger_mux_o : out t_wishbone_slave_out_array(g_num_mux_interfaces-1 downto 0);
-----------------------------
-- External ports
-----------------------------
trig_b : inout std_logic_vector(g_trig_num-1 downto 0);
trig_dir_o : out std_logic_vector(g_trig_num-1 downto 0);
-----------------------------
-- Internal ports
-----------------------------
trig_rcv_intern_i : in t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_rcv_intern_num-1 downto 0); -- signals from inside the FPGA that can be used as input at a rcv mux
trig_pulse_transm_i : in t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_intern_num-1 downto 0);
trig_pulse_rcv_o : out t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_intern_num-1 downto 0)
);
end xwb_trigger;
architecture rtl of xwb_trigger is
-- Trigger 2d <-> 1d conversion
signal trig_rcv_intern_compat : t_trig_channel_array(g_num_mux_interfaces*g_rcv_intern_num-1 downto 0);
-- Trigger 2d <-> 1d conversion
signal trig_pulse_transm_compat : t_trig_channel_array(g_num_mux_interfaces*g_intern_num-1 downto 0);
signal trig_pulse_rcv_compat : t_trig_channel_array(g_num_mux_interfaces*g_intern_num-1 downto 0);
signal wb_slv_trigger_mux_adr_in_int : std_logic_vector(g_num_mux_interfaces*c_wishbone_address_width-1 downto 0);
signal wb_slv_trigger_mux_dat_in_int : std_logic_vector(g_num_mux_interfaces*c_wishbone_data_width-1 downto 0);
signal wb_slv_trigger_mux_dat_out_int : std_logic_vector(g_num_mux_interfaces*c_wishbone_data_width-1 downto 0);
signal wb_slv_trigger_mux_sel_in_int : std_logic_vector(g_num_mux_interfaces*c_wishbone_data_width/8-1 downto 0);
signal wb_slv_trigger_mux_we_in_int : std_logic_vector(g_num_mux_interfaces-1 downto 0);
signal wb_slv_trigger_mux_cyc_in_int : std_logic_vector(g_num_mux_interfaces-1 downto 0);
signal wb_slv_trigger_mux_stb_in_int : std_logic_vector(g_num_mux_interfaces-1 downto 0);
signal wb_slv_trigger_mux_ack_out_int : std_logic_vector(g_num_mux_interfaces-1 downto 0);
signal wb_slv_trigger_mux_err_out_int : std_logic_vector(g_num_mux_interfaces-1 downto 0);
signal wb_slv_trigger_mux_rty_out_int : std_logic_vector(g_num_mux_interfaces-1 downto 0);
signal wb_slv_trigger_mux_stall_out_int : std_logic_vector(g_num_mux_interfaces-1 downto 0);
begin
cmp_wb_trigger : wb_trigger
generic map (
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_sync_edge => g_sync_edge,
g_trig_num => g_trig_num,
g_intern_num => g_intern_num,
g_rcv_intern_num => g_rcv_intern_num,
g_num_mux_interfaces => g_num_mux_interfaces,
g_out_resolver => g_out_resolver,
g_in_resolver => g_in_resolver,
g_with_input_sync => g_with_input_sync,
g_with_output_sync => g_with_output_sync
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
ref_clk_i => ref_clk_i,
ref_rst_n_i => ref_rst_n_i,
fs_clk_array_i => fs_clk_array_i,
fs_rst_n_array_i => fs_rst_n_array_i,
wb_trigger_iface_adr_i => wb_slv_trigger_iface_i.adr,
wb_trigger_iface_dat_i => wb_slv_trigger_iface_i.dat,
wb_trigger_iface_dat_o => wb_slv_trigger_iface_o.dat,
wb_trigger_iface_sel_i => wb_slv_trigger_iface_i.sel,
wb_trigger_iface_we_i => wb_slv_trigger_iface_i.we,
wb_trigger_iface_cyc_i => wb_slv_trigger_iface_i.cyc,
wb_trigger_iface_stb_i => wb_slv_trigger_iface_i.stb,
wb_trigger_iface_ack_o => wb_slv_trigger_iface_o.ack,
wb_trigger_iface_err_o => wb_slv_trigger_iface_o.err,
wb_trigger_iface_rty_o => wb_slv_trigger_iface_o.rty,
wb_trigger_iface_stall_o => wb_slv_trigger_iface_o.stall,
wb_trigger_mux_adr_i => wb_slv_trigger_mux_adr_in_int,
wb_trigger_mux_dat_i => wb_slv_trigger_mux_dat_in_int,
wb_trigger_mux_dat_o => wb_slv_trigger_mux_dat_out_int,
wb_trigger_mux_sel_i => wb_slv_trigger_mux_sel_in_int,
wb_trigger_mux_we_i => wb_slv_trigger_mux_we_in_int,
wb_trigger_mux_cyc_i => wb_slv_trigger_mux_cyc_in_int,
wb_trigger_mux_stb_i => wb_slv_trigger_mux_stb_in_int,
wb_trigger_mux_ack_o => wb_slv_trigger_mux_ack_out_int,
wb_trigger_mux_err_o => wb_slv_trigger_mux_err_out_int,
wb_trigger_mux_rty_o => wb_slv_trigger_mux_rty_out_int,
wb_trigger_mux_stall_o => wb_slv_trigger_mux_stall_out_int,
trig_b => trig_b,
trig_dir_o => trig_dir_o,
trig_rcv_intern_i => trig_rcv_intern_compat,
trig_pulse_transm_i => trig_pulse_transm_compat,
trig_pulse_rcv_o => trig_pulse_rcv_compat
);
gen_wb_slv_trigger_interfaces : for i in 0 to g_num_mux_interfaces-1 generate
wb_slv_trigger_mux_adr_in_int((i+1)*c_wishbone_address_width-1 downto i*c_wishbone_address_width) <= wb_slv_trigger_mux_i(i).adr;
wb_slv_trigger_mux_sel_in_int((i+1)*c_wishbone_data_width/8-1 downto i*c_wishbone_data_width/8) <= wb_slv_trigger_mux_i(i).sel;
wb_slv_trigger_mux_dat_in_int((i+1)*c_wishbone_data_width-1 downto i*c_wishbone_data_width) <= wb_slv_trigger_mux_i(i).dat;
wb_slv_trigger_mux_cyc_in_int(i) <= wb_slv_trigger_mux_i(i).cyc;
wb_slv_trigger_mux_stb_in_int(i) <= wb_slv_trigger_mux_i(i).stb;
wb_slv_trigger_mux_we_in_int(i) <= wb_slv_trigger_mux_i(i).we;
wb_slv_trigger_mux_o(i).dat <= wb_slv_trigger_mux_dat_out_int((i+1)*c_wishbone_data_width-1 downto i*c_wishbone_data_width);
wb_slv_trigger_mux_o(i).ack <= wb_slv_trigger_mux_ack_out_int(i);
wb_slv_trigger_mux_o(i).stall <= wb_slv_trigger_mux_stall_out_int(i);
wb_slv_trigger_mux_o(i).err <= wb_slv_trigger_mux_err_out_int(i);
wb_slv_trigger_mux_o(i).rty <= wb_slv_trigger_mux_rty_out_int(i);
end generate;
-- Convert 1d <-> 2d vectors
gen_compat_interfaces : for i in 0 to g_num_mux_interfaces-1 generate
gen_rcv_intern_compat_trigger_channels : for j in 0 to g_rcv_intern_num-1 generate
trig_rcv_intern_compat(i*g_rcv_intern_num + j) <= trig_rcv_intern_i(i, j);
end generate;
gen_compat_trigger_channels : for j in 0 to g_intern_num-1 generate
trig_pulse_transm_compat(i*g_intern_num + j) <= trig_pulse_transm_i(i, j);
trig_pulse_rcv_o(i, j) <= trig_pulse_rcv_compat(i*g_intern_num + j);
end generate;
end generate;
end rtl;
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files = [
"wb_trigger_iface.vhd",
"xwb_trigger_iface.vhd",
"wbgen/wb_trigger_iface_regs.vhd",
"wbgen/wb_trigger_iface_regs_pkg.vhd"];
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#!/bin/bash
wbgen2 -V wb_trigger_iface_regs.vhd -H record -p wb_trigger_iface_regs_pkg.vhd -K ../../../../sim/regs/wb_trigger_iface_regs.vh -s defines -C wb_trigger_iface_regs.h -f html -D doc/wb_trigger_iface_regs_wb.html wb_trigger_iface.wb
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all;
-- Trigger definitions
use work.trigger_pkg.all;
entity xwb_trigger_iface is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_sync_edge : string := "positive";
g_trig_num : natural range 1 to 24 := 8
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
ref_clk_i : in std_logic;
ref_rst_n_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- External ports
-----------------------------
trig_b : inout std_logic_vector(g_trig_num-1 downto 0);
trig_dir_o : out std_logic_vector(g_trig_num-1 downto 0);
-----------------------------
-- Internal ports
-----------------------------
trig_out_o : out t_trig_channel_array(g_trig_num-1 downto 0);
trig_in_i : in t_trig_channel_array(g_trig_num-1 downto 0)
);
end xwb_trigger_iface;
architecture rtl of xwb_trigger_iface is
begin
cmp_wb_trigger_iface : wb_trigger_iface
generic map (
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_sync_edge => g_sync_edge,
g_trig_num => g_trig_num
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
ref_clk_i => ref_clk_i,
ref_rst_n_i => ref_rst_n_i,
wb_adr_i => wb_slv_i.adr,
wb_dat_i => wb_slv_i.dat,
wb_dat_o => wb_slv_o.dat,
wb_sel_i => wb_slv_i.sel,
wb_we_i => wb_slv_i.we,
wb_cyc_i => wb_slv_i.cyc,
wb_stb_i => wb_slv_i.stb,
wb_ack_o => wb_slv_o.ack,
wb_err_o => wb_slv_o.err,
wb_rty_o => wb_slv_o.rty,
wb_stall_o => wb_slv_o.stall,
trig_b => trig_b,
trig_dir_o => trig_dir_o,
trig_out_o => trig_out_o,
trig_in_i => trig_in_i
);
end rtl;
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files = [
"wb_trigger_mux.vhd",
"xwb_trigger_mux.vhd",
"wbgen/wb_trigger_mux_regs.vhd",
"wbgen/wb_trigger_mux_regs_pkg.vhd"];
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#!/bin/bash
wbgen2 -V wb_trigger_mux_regs.vhd -H record -p wb_trigger_mux_regs_pkg.vhd -K ../../../../sim/regs/wb_trigger_mux_regs.vh -s defines -C wb_trigger_mux_regs.h -f html -D doc/wb_trigger_mux_regs_wb.html wb_trigger_mux.wb
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files = [
"icon_4_port/chipscope_icon_4_port.ngc",
"icon_1_port/chipscope_icon_1_port.ngc",
"icon_1_port/chipscope_icon_1_port.vhd",
"icon_2_port/chipscope_icon_2_port.ngc",
"icon_2_port/chipscope_icon_2_port.vhd",
"icon_4_port/chipscope_icon_4_port.ngc",
"icon_4_port/chipscope_icon_4_port.vhd",
"icon_6_port/chipscope_icon_6_port.ngc",
"icon_6_port/chipscope_icon_6_port.vhd",
"ila/chipscope_ila.ngc",
"ila/chipscope_ila.vhd"]
"ila/chipscope_ila.vhd",
"ila/chipscope_ila_rcv.ngc",
"ila/chipscope_ila_rcv.vhd",
"vio/chipscope_vio_32.vhd",
"vio/chipscope_vio_32.ngc",
"vio/chipscope_vio_16.vhd",
"vio/chipscope_vio_16.ngc",
"vio/chipscope_vio_8.vhd",
"vio/chipscope_vio_8.ngc"]
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-------------------------------------------------------------------------------
-- Copyright (c) 2016 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_icon_1_port.vhd
-- /___/ /\ Timestamp : Thu Feb 04 13:05:59 BRST 2016
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_icon_1_port IS
port (
CONTROL0: inout std_logic_vector(35 downto 0));
END chipscope_icon_1_port;
ARCHITECTURE chipscope_icon_1_port_a OF chipscope_icon_1_port IS
BEGIN
END chipscope_icon_1_port_a;
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