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## Main features
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- **Programmable resources:**
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- Xilinx Kintex-7 325T FFG900 FPGA
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- 2 GB DDR3 SDRAM (32-bit interface)
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- 2 high pin count (HPC) slots for 2 single width mezzanines or 1
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double width
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mezzanine
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- MMC: LPC1764FBD100, optionally Atxmega128A1U-AU
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<!-- end list -->
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- **Memory:**
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- 2 GB DDR3 SDRAM (32-bit interface), 800Mhz
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- SPI Flash for FPGA configuration
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- SPI Flash for user data storage
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- JTAG multiplexer (SCANSTA) for FMC access
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- Power supply for FPGA, memory, FMCs - programmable VADJ 1.8-3.3V
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- Clock distribution circuit compatible with WR
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- Temperature, voltage and current monitoring for critical power buses
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- Stand-alone power connector
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- EEPROM with MAC and unique ID
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<!-- end list -->
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- **Connectivity:**
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- 2 high pin count (HPC) slots for 2 single width mezzanines or 1
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double width mezzanine
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- Mini-USB UART connected to FPGA or MMC
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- Mini-USB connected to the IPMI processor
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- Stand-alone power connector(12V, 3.3V aux)
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- SATA connector for Port2, Port3 with possibility of switching to
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FPGA MGT
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- MGT connected to FMC1, FMC2, Fat Pipe 1, Fat Pipe 2 (optional),
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Port0, Port1,
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Port2 (optional), Port3 (optional), RTM (optional)
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- EEPROM with MAC and unique ID
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Port0, Port1, Port2 (optional), Port3 (optional), RTM (optional)
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- RTM connector with 8 GTP routed to it. Compatible with rtm-sfp8
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module.
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- **Supply:**
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- Power supply for FPGA, memory, FMCs - programmable VADJ 1.8-3.3V
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(independent for each FMC)
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- Voltage and current monitoring for all FMC power buses
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- Clock distribution circuit compatible with WR
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<!-- end list -->
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- **Other:**
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- Temperature monitoring: FMC1, FMC2, supply, FPGA core, DDR
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memory
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- JTAG multiplexer (SCANSTA) for FMC access
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-----
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## Detailed project information
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-----
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Filip Świtakowski - 18 Aug 2014
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Filip Świtakowski - 08 Oct 2014
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