Commit 71e715b9 authored by Tomasz Przywózki's avatar Tomasz Przywózki

v4.0rc2

parent b88ec831
......@@ -1712,36 +1712,6 @@ OutputName11=Specctra Design PCB
OutputDocumentPath11=
OutputVariantName11=
OutputDefault11=0
OutputType12=Ansoft Neutral
OutputName12=Ansoft Neutral (AutoPCB)
OutputDocumentPath12=
OutputVariantName12=
OutputDefault12=0
OutputType13=HyperLynx
OutputName13=HyperLynx (AutoPCB)
OutputDocumentPath13=
OutputVariantName13=
OutputDefault13=0
OutputType14=Orcad v7 Capture Design
OutputName14=Orcad v7 Capture Design (AutoSCH)
OutputDocumentPath14=
OutputVariantName14=
OutputDefault14=0
OutputType15=P-CAD ASCII
OutputName15=P-CAD ASCII (AutoPCB)
OutputDocumentPath15=
OutputVariantName15=
OutputDefault15=0
OutputType16=P-CAD V16 Schematic Design
OutputName16=P-CAD V16 Schematic Design (AutoSCH)
OutputDocumentPath16=
OutputVariantName16=
OutputDefault16=0
OutputType17=SiSoft
OutputName17=SiSoft (AutoPCB)
OutputDocumentPath17=
OutputVariantName17=
OutputDefault17=0
[OutputGroup10]
Name=PostProcess Outputs
......
  • Added cutout on ground layers (under GTP caps).

    Swapped power layers P3 <-> G2

    Deleted old stackup table (top layer)

    Edited by Tomasz Przywózki
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