- Jul 06, 2020
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Tomasz Przywózki authored
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- Jul 03, 2020
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Tomasz Przywózki authored
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- Jul 01, 2020
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Tomasz Przywózki authored
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- Jun 30, 2020
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Tomasz Przywózki authored
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- Jun 24, 2020
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Tomasz Przywózki authored
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- Jun 11, 2020
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Tomasz Przywózki authored
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- Jun 10, 2020
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Tomasz Przywózki authored
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- Jun 09, 2020
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Tomasz Przywózki authored
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Tomasz Przywózki authored
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- Jun 08, 2020
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Tomasz Przywózki authored
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- Jun 02, 2020
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Tomasz Przywózki authored
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- May 27, 2020
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Tomasz Przywózki authored
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- Jun 03, 2015
- Aug 01, 2014
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Filip Świtakowski authored
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- May 16, 2014
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Greg authored
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- Apr 04, 2014
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Greg authored
Added OHL license on the schematics updated mounted/not mounted designators.
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- Feb 21, 2014
- Feb 10, 2014
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Greg authored
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- Jan 29, 2014
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Greg authored
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- Jan 02, 2014
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Greg authored
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- Jan 01, 2014
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Greg authored
All RC come from CERN library Seriously limited BOM Almost all issues solved PCB - acute angles removed improved plane layout- limited cutouts over high speed signals added OutJob file
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- Nov 25, 2013
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Greg authored
P3V3 aux regulator added in stand-alone mode Port0/1 and 2-lane FP2 operation now possible quad 116 connected to the clock crossbar lot of small bugs fixed according to "issues" list
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- Nov 24, 2013
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Greg authored
inverted all HPC lines
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- Nov 05, 2013
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Greg authored
detected swapped RTM connectors - some work need to be done on layout version without polygons to reduce PCB size and to make checking easier
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- Nov 04, 2013
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Greg authored
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- Nov 03, 2013
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Greg authored
wrong voltage measurement on FMC P12V - before the switch Added JTAG support for RTM_CON Added RTM power switches and I2C buffer moved both USB ports to the front panel swapped GTP - FP1 and FP2 to optimize FPGA timings cleaned net names in GTP schematic
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- Oct 25, 2013
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Greg authored
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- Aug 26, 2013
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Greg authored
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