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Absolute Encoder VHDL core
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Absolute Encoder VHDL core
Commits
7ad46c48
Commit
7ad46c48
authored
Nov 25, 2015
by
Fabien Le Mentec
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hdl, absenc: BISS master waits for start bit
parent
6d4e5e3f
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2 changed files
with
6 additions
and
5 deletions
+6
-5
user.tcl
sim/isim/user.tcl
+2
-2
absenc_master_biss.vhd
src/absenc_master_biss.vhd
+4
-3
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sim/isim/user.tcl
View file @
7ad46c48
# source endat.tcl
# source endat.tcl
#
source biss.tcl
source
biss.tcl
source
ssi.tcl
#
source ssi.tcl
# wave add /main/master/latched_data
# wave add /main/master/latched_data
# wave add /main/master/msb_data
# wave add /main/master/msb_data
...
...
src/absenc_master_biss.vhd
View file @
7ad46c48
...
@@ -113,7 +113,7 @@ begin
...
@@ -113,7 +113,7 @@ begin
end
process
;
end
process
;
process
(
curr_state
,
count_match
,
tm_match
)
process
(
curr_state
,
count_match
,
tm_match
,
miso
)
begin
begin
next_state
<=
curr_state
;
next_state
<=
curr_state
;
...
@@ -131,8 +131,9 @@ begin
...
@@ -131,8 +131,9 @@ begin
next_state
<=
BISS_START
;
next_state
<=
BISS_START
;
when
BISS_START
=>
when
BISS_START
=>
-- TODO: check miso == 1
if
miso
=
'1'
then
next_state
<=
BISS_CDS
;
next_state
<=
BISS_CDS
;
end
if
;
when
BISS_CDS
=>
when
BISS_CDS
=>
next_state
<=
BISS_DATA
;
next_state
<=
BISS_DATA
;
...
...
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