hdl, absenc: BISS master waits for start bit

7ad46c48 · Fabien Le Mentec · 6d4e5e3f · 7ad46c48 · 7ad46c48
Commit 7ad46c48 authored Nov 25, 2015 by Fabien Le Mentec
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Showing with 6 additions and 5 deletions

user.tcl sim/isim/user.tcl +2 -2

absenc_master_biss.vhd src/absenc_master_biss.vhd +4 -3

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--- a/sim/isim/user.tcl
+++ b/sim/isim/user.tcl
 # source endat.tcl
-# source biss.tcl
-source ssi.tcl
+source biss.tcl
+# source ssi.tcl

 # wave add /main/master/latched_data
 # wave add /main/master/msb_data

--- a/src/absenc_master_biss.vhd
+++ b/src/absenc_master_biss.vhd
@@ -113,7 +113,7 @@ begin
 end process;


-process(curr_state, count_match, tm_match)
+process(curr_state, count_match, tm_match, miso)
 begin
 
 next_state <= curr_state;
@@ -131,8 +131,9 @@ begin
   next_state <= BISS_START;

  when BISS_START =>
-   -- TODO: check miso == 1
-   next_state <= BISS_CDS;
+   if miso = '1' then
+    next_state <= BISS_CDS;
+   end if;

  when BISS_CDS =>
   next_state <= BISS_DATA;