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# VME64x to Wishbone Core
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## Project description
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The VME64x core implements a VME64 slave on one side and a WishBone
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master on the other without FIFOs in-between.
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The core supports SINGLE, BLT (D32), MBLT (D64), 2eVME and 2eSST
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transfers in A24, A32 and A64 address modes and D08 (OE), D16, D32, D64
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data transfers. The core can be configured via implemented CR/CSR
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configuration space. A ROACK type IRQ controller with one interrupt
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input and a programmable interrupt level and Status/ID register is
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provided.
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A WishBone side features a pipelined WB master for SINGLE
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transfers.
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-----
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## Main features
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- VME64x slave
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- CR/CSR space
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- ROACK type IRQ controller with one interrupt input and a
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programmable interrupt level and Status/ID register
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- Supported VME access modes
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- SINGLE, BLT (D32), MBLT (D64)
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- A24, A32 and A64 address modes and D08 (OE), D16, D32, D64
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data transfers
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- WishBone master (user side)
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- Pipelined WB master for SINGLE transfers
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-----
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## Project information
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- [VME64x user
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manual](https://www.ohwr.org/project/vme64x-core/commits/master/documentation/user_guides/vme64x_user_manual.pdf)
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- [VME access
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modes](https://www.ohwr.org/project/vme64x-core/blob/master/documentation/user_guides/VME_access_modes.pdf)
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- [Guidelines to use the vme64x
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core](https://www.ohwr.org/project/vme64x-core/blob/master/documentation/user_guides/Python_test.pdf)
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- [*Design, implementation and test of a VME to Wishbone
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interface*](https://www.ohwr.org/project/vme64x-core/wikis/Documents/Design-implementation-and-test-of-a-VME-to-WB-interface), Thesis of Davide
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Pedretti
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- [Users](Users)
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- [Frequently Asked Questions](FAQ)
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-----
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## Documents
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- [Wishbone System-on-chip (SoC) Interconnection Architecture for
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Portable IP Cores, Revision
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B4](http://cdn.opencores.org/downloads/wbspec_b4.pdf)
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- VME64 ANSI/VITA 1 1994
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- VME64 Extensions ANSI/VITA 1.1 1997
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- ANSI/VITA 1.5-2003 2eSST
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-----
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## Contacts
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### General question about project
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- [Erik van der Bij](mailto:Erik.van.der.Bij@cern.ch) - CERN
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-----
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## Project Status
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Date</strong></td>
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<td><b> Event </b></td>
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</tr>
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<tr class="even">
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<td>01-04-2010</td>
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<td>Start working on project.</td>
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</tr>
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<tr class="odd">
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<td>25-05-2010</td>
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<td>First HDL release.</td>
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</tr>
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<tr class="even">
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<td>10-02-2011</td>
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<td>First register read/write made with the core on the VFC.</td>
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</tr>
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<tr class="odd">
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<td>01-02-2012</td>
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<td>New student will work full time on project.</td>
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</tr>
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<tr class="even">
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<td>03-05-2012</td>
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<td>Core has been modified to implement CSR space. CSR and single R/W working on [VFC V2](https://www.ohwr.org/project/fmc-vme-carrier/wiki).</td>
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</tr>
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<tr class="odd">
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<td>10-05-2012</td>
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<td>Working on BLT, MBLT and 2eSST implementation.</td>
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</tr>
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<tr class="even">
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<td>06-06-2012</td>
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<td>Added data swap modes. A64, 2eVME and 2eSST not yet implemented. Independent tester added to team.</td>
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</tr>
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<tr class="odd">
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<td>30-07-2012</td>
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<td>SINGLE, BLT (D32), MBLT (D64) transfers in A16, A24, A32 and A64 address modes working<br />
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on VFC V2 and SVEC V0. A ROACK type IRQ Controller is provided.</td>
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</tr>
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<tr class="even">
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<td>30-11-2012</td>
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<td>Student Davide Pedretti left CERN. <a href="https://www.ohwr.org/project/vme64x-core/wikis/Documents/Design-implementation-and-test-of-a-VME-to-WB-interface">Thesis</a> available. Core works.</td>
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</tr>
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<tr class="odd">
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<td>07-03-2013</td>
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<td>Several bugs found and corrected. Core is working, but needs a good review.</td>
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</tr>
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<tr class="even">
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<td>01-07-2013</td>
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<td>Migrated the repository to Git.</td>
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</tr>
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<tr class="odd">
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<td>29-05-2013</td>
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<td>Core re-used as basis for design at GSI.</td>
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</tr>
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<tr class="even">
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<td>29-11-2013</td>
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<td>Bug <a href="https://www.ohwr.org/project/vme64x-core/issues/16">multiple cards DTACKing on same CSR address</a> found.</td>
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</tr>
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<tr class="odd">
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<td>11-12-2013</td>
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<td>Decided to start in 2014 a new project to rewrite/cleanup the core to make it better maintainable.</td>
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</tr>
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<tr class="even">
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<td>20-10-2014</td>
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<td>Project in same state as in 2013 and used reliably in many places.</td>
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</tr>
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<tr class="odd">
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<td>20-10-2014</td>
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<td>Found issue with [WB error handling](https://www.ohwr.org/project/vme64x-core/issues/13).</td>
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</tr>
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</tbody>
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</table>
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-----
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Davide Pedretti, Erik van der Bij, Tomasz Wlostowski - 9 April 2015
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