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Mathieu Saccani
VME64x core - msaccani
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adam-ci
5bd45fd2
·
hdl/testbench/Makefile: support slashes in TB_DIRS
·
Dec 15, 2017
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tom-bridge-nov27
9d52c5c1
·
adding missing files
·
Dec 11, 2019
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tom-cvora-feb10
ffa531dc
·
vme_bus: don't go to CHECK_TRANSFER_TYPE if DS inactive, causes an infinite loop
·
Feb 11, 2020
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tg-prefetch
48a4a5db
·
vme_funct_match: fix the function priority encoder.
·
Apr 15, 2020
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master
default
protected
def8d371
·
vme_bus: 2eSST improvements.
·
Jun 04, 2020
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cvora-jul15
6d2b770e
·
hdl: improved static generation of ADER regsisters (non-64x mode with base address switch)
·
Jul 15, 2020
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patch-1
ec2b1e38
·
Change the generic assignment per index/field in a record type, because it is...
·
Jul 20, 2020
project/vme64x-core!1
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undefined
0d5b625b
·
VME Core 64x wrapper for Verilog instantiation.
·
Jul 20, 2020
project/vme64x-core!2
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dab64x
61d6769b
·
Remove the glitch observed on dtack in MBLT mode (seen on Dab64x at 40MHz with MEN-A20).
·
Dec 07, 2020
!1
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dab64x_shared_vme
2f199fec
·
Leave card_sel open
·
Dec 07, 2020
project/vme64x-core!4
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patch-2
7bef6e0a
·
Remove the glitch observed on dtack in MBLT mode (seen on Dab64x at 40MHz with MEN-A20).
·
Dec 07, 2020
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patch-3
20629818
·
Add some missing reset values, so the signals propagated to the WB are not 'X'...
·
Oct 19, 2023
project/vme64x-core!11
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