Commit b3e03396 authored by Matthieu Cattin's avatar Matthieu Cattin

Modify test04 to verify that Si570 output frequency is within the limits.…

Modify test04 to verify that Si570 output frequency is within the limits. Instead of just checking Si570 registers value, that might be different from chip to chip.
parent a3a07278
......@@ -624,9 +624,16 @@ class CFmcAdc100Ms:
# Get Si570 config
def get_si570_config(self):
return self.si570.get_rfreq(), self.si570.get_n1_div(), self.si570.get_hs_div()
"""
config = []
config.append(self.si570.get_rfreq())
config.append(self.si570.get_n1_div())
config.append(self.si570.get_hs_div())
return config
"""
# Get Si570 raw config (hex value of the I2C registers in a table)
def get_si570_raw_config(self):
return self.si570.get_raw_config()
......@@ -30,6 +30,7 @@ class CSi57x:
FDCO_FREEZE_DCO = (1<<4)
HS_DIV = [4, 5, 6, 7, 0, 9, 0, 11]
def __init__(self, i2c, addr):
self.i2c = i2c
......@@ -59,10 +60,10 @@ class CSi57x:
def get_n1_div(self):
n1 = ((self.rd_reg(self.R_RFREQ4) & self.N1_L_MASK)>>6)
n1 += ((self.rd_reg(self.R_HS) & self.N1_H_MASK)<<2)
return n1
return n1+1
def get_hs_div(self):
return ((self.rd_reg(self.R_HS))>>5)
return self.HS_DIV[((self.rd_reg(self.R_HS))>>5)]
def set_rfreq(self, freq):
self.wr_reg(self.R_RFERQ0, (freq & 0xFF))
......@@ -104,6 +105,16 @@ class CSi57x:
reg = self.rd_reg(self.R_RFMC) | self.RFMC_RECALL
self.wr_reg(self.R_RFMC, reg)
def get_raw_config(self):
config = []
config.append(self.rd_reg(self.R_HS))
config.append(self.rd_reg(self.R_RFREQ4))
config.append(self.rd_reg(self.R_RFREQ3))
config.append(self.rd_reg(self.R_RFREQ2))
config.append(self.rd_reg(self.R_RFREQ1))
config.append(self.rd_reg(self.R_RFREQ0))
return config
# For Si571 only !
def freeze_vcadc(self):
reg = self.rd_reg(self.R_RFMC) | self.RFMC_FREEZE_VCADC
......
......@@ -22,6 +22,11 @@ Note: Requires test00.py to run first to load the firmware!
"""
SI570_ADDR = 0x55
SI570_XTAL_FREQ_MIN = 114.056
SI570_XTAL_FREQ_MAX = 114.514
SI570_FOUT = 100.000
SI570_FOUT_TOL = 1.0
SI570_RFREQ = 42
SI570_N1 = 7
SI570_HS_DIV = 2
......@@ -58,19 +63,34 @@ def main (default_directory='.'):
raise PtsError('Wrong device mounted on I2C bus, address is:0x%.2X expected:0x%.2X'%(periph_addr[0],SI570_ADDR))
# Get Si570 configuration
si570_config = fmc.get_si570_config()
rfreq, n1, hs_div = fmc.get_si570_config()
print("\nPrint Si570 configuration")
print("RFREQ : %3.28f") % si570_config[0]
print("N1 : %d") % si570_config[1]
print("HS_DIV : %d") % si570_config[2]
# Check Si570 configuration
if(int(si570_config[0]) != SI570_RFREQ):
raise PtsError('Si570 bad reference frequency configured or wrong part is mounted')
if(si570_config[1] != SI570_N1):
raise PtsError('Si570 CLKOUT output divider is badly configured or wrong part is mounted')
if(si570_config[2] != SI570_HS_DIV):
raise PtsError('Si570 DCO high speed divider is badly configured or wrong part is mounted')
print("RFREQ : %3.28f") % rfreq
print("N1 : %d") % n1
print("HS_DIV : %d") % hs_div
# Check that HS_DIV is different from 0
# If HS_DIV register value is "100" or "110" (not used) get_si570_config returns 0
if (hs_div == 0):
raise PtsError('Si570 invalid HS_DIV value')
# Calculate min and max output frequency based on the min and max xtal frequency
# See http://cp-siliconlabs.kb.net/article.aspx?article=311398&p=12972
f_out_min = (SI570_XTAL_FREQ_MIN * rfreq) / (float(n1) * float(hs_div))
f_out_max = (SI570_XTAL_FREQ_MAX * rfreq) / (float(n1) * float(hs_div))
print("FOUT_MIN : %3.3f") % f_out_min
print("FOUT_MAX : %3.3f") % f_out_max
# Check that output frequency is within the limits
f_out_limit_min = SI570_FOUT - SI570_FOUT_TOL
f_out_limit_max = SI570_FOUT + SI570_FOUT_TOL
print("FOUT_LIMIT_MIN : %3.3f") % f_out_limit_min
print("FOUT_LIMIT_MAX : %3.3f") % f_out_limit_max
if (f_out_limit_min < f_out_min) and (f_out_min < SI570_FOUT) and (SI570_FOUT < f_out_max) and (f_out_max < f_out_limit_max):
print("Si570 frequency output is within tolerance")
else:
raise PtsError('Si570 frequency output is outside of the tolerance')
if __name__ == '__main__' :
......
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