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Commit a3a07278 authored by Matthieu Cattin's avatar Matthieu Cattin
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Fix bug in trigger configuration.

parent 77d6683d
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Showing with 10 additions and 6 deletions
test/fmcadc100m14b4cha/python/fmc_adc.py
View file @ a3a07278
......@@ -146,8 +146,8 @@ class CFmcAdc100Ms:
TRIG_CFG_INT_SEL = 4
TRIG_CFG_INT_THRES = 16
INT_SEL_MASK = 0x00000030
INT_THRES_MASK = 0xFFFF0000
INT_SEL_MASK = 0xFFFFFFCF
INT_THRES_MASK = 0x0000FFFF
IN_TERM = (1<<3)
IN_TERM_MASK = 0x08
......@@ -446,11 +446,13 @@ class CFmcAdc100Ms:
self.fmc_adc_csr.wr_bit(self.R_TRIG_CFG, self.TRIG_CFG_SW_EN, sw_en)
# Internal trigger channel select (1 to 4)
reg = self.fmc_adc_csr.rd_reg(self.R_TRIG_CFG)
reg |= ((int_sel<<self.TRIG_CFG_INT_SEL) & self.INT_SEL_MASK)
reg &= self.INT_SEL_MASK
reg += (int_sel<<self.TRIG_CFG_INT_SEL)
self.fmc_adc_csr.wr_reg(self.R_TRIG_CFG, reg)
# Internal trigger threshold
reg = self.fmc_adc_csr.rd_reg(self.R_TRIG_CFG)
reg |= ((int_thres<<self.TRIG_CFG_INT_THRES) & self.INT_THRES_MASK)
reg &= self.INT_THRES_MASK
reg += (int_thres<<self.TRIG_CFG_INT_THRES)
self.fmc_adc_csr.wr_reg(self.R_TRIG_CFG, reg)
# Trigger delay (in sampling clock ticks)
self.fmc_adc_csr.wr_reg(self.R_TRIG_DLY, delay)
......@@ -467,11 +469,13 @@ class CFmcAdc100Ms:
self.fmc_adc_csr.wr_bit(self.R_TRIG_CFG, self.TRIG_CFG_EXT_POL, polarity)
# Internal trigger channel select (1 to 4)
reg = self.fmc_adc_csr.rd_reg(self.R_TRIG_CFG)
reg |= (((channel-1)<<self.TRIG_CFG_INT_SEL) & self.INT_SEL_MASK)
reg &= self.INT_SEL_MASK
reg += (int_sel<<self.TRIG_CFG_INT_SEL)
self.fmc_adc_csr.wr_reg(self.R_TRIG_CFG, reg)
# Internal trigger threshold
reg = self.fmc_adc_csr.rd_reg(self.R_TRIG_CFG)
reg |= ((threshold<<self.TRIG_CFG_INT_THRES) & self.INT_THRES_MASK)
reg &= self.INT_THRES_MASK
reg += (int_thres<<self.TRIG_CFG_INT_THRES)
self.fmc_adc_csr.wr_reg(self.R_TRIG_CFG, reg)
# Hardware trigger enable
self.fmc_adc_csr.wr_bit(self.R_TRIG_CFG, self.TRIG_CFG_HW_EN, 1)
......
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