* read and write byte functions.
    * page write function with size and page boundary check.
    * sequencial read function.

Apply changes made by Richard to the eeprom_24aa64 module.

    Changes made by Richard Carrillo (7solutions) for the fmcdio5chttla.
        * Proper exception raising and handling.
        * Avoiding infinite loop by adding timeouts.

Some cleanup in the comments and commented debug messages.

    Changes made by Richard Carrillo (7solutions) for the fmcdio5chttla.
    * Proper exception raising and handling.
    * Avoiding infinite loop by adding timeouts.

Fix a bug introduced in the scan function.
Was not scanning the last address and sending write instead of read operation.

Some cleanup in the comments and commented debug messages.

Changes made by Richard Carrillo (7solutions) for the fmcdio5chttla.
* Proper exception raising and handling.
* Avoiding infinite loop by adding timeouts.

Some cleanup in the comments and commented debug messages.

This function is used by the fmc_delay C library.

Add a first set of common modules from fmcadc100m14b4cha.

Fix C shared library path in rr.py
Remove undefined rr_read and rr_write from rrlib.h
Remove rr.py and rrlib.so from pts root directory.
Put updated versions of rr.py, rrlib.so and rr_loader_lib.so in
test/fmcadc100m14b4cha/python those should be removed when all
tests will use common modules.

Library features are:
- Gennum GPIO configuration
- SPEC boot mode selection (Gennum to FPAG, Genum to Flash or Flash to FPGA)
- Bit bang SPI programming/erase/readback of the Flash
- Force FPGA reload from flash
- FPGA firmware loading using Gennum FCL (= FPGA Configuration Loader)

Function to load FPGA firmware from Gennum added to Python wrapper rr.py

Added the generation of the libfpga_loader shared library. And
comment the output messages of the fpga_loader.

This fpga_loader is only valid for SPEC V2.0 or higher.

The timeout was setup to 1 second (HZ constant in jiffies) to fix a problem
in the test/spec/python/test07.py.

This test file was always waiting for the IRQ from the first DMA.

The DMA transfer was properly finished but the IRQ doesn't arrive. It seems
that the problem behind is a wrong initialization (reset?) of the corresponding
DMA core in the Firmware.

This is a workaround of the problem.