Work on ltc217x module.

Adding more function for configuration.

common/ltc217x.py

-#!/usr/bin/python
+#!   /usr/bin/env   python
+#    coding: utf8
 
+# Copyright CERN, 2011
+# Author: Matthieu Cattin (CERN)
+# Licence: GPL v2 or later.
+# Website: http://www.ohwr.org
+# Last modifications: 27/4/2012
+
+# Import standard modules
 import sys
-import rr
 import time
+
+# Import specific modules
+import rr
 import spi
 
+# Class to access the LTC217x (ADC) chip.
+# It uses the SPI class.
+
 class CLTC217x:
 
+    # LTC217x registers
     R_RST = 0x00
     R_FMT = 0x01
     R_OUTMODE = 0x02
@@ -24,32 +38,27 @@ class CLTC217x:
     FMT_CH2_NAP = (1<<1)
     FMT_CH1_NAP = (1<<0)
 
-    OUTMODE_ILVDS_3M5 = (0<<5)
-    OUTMODE_ILVDS_4M0 = (1<<5)
-    OUTMODE_ILVDS_4M5 = (2<<5)
-    OUTMODE_ILVDS_3M0 = (4<<5)
-    OUTMODE_ILVDS_2M5 = (5<<5)
-    OUTMODE_ILVDS_2M1 = (6<<5)
-    OUTMODE_ILVDS_1M75 = (7<<5)
+    OUTMODE_ILVDS_MASK = 0xE0
     OUTMODE_TERMON = (1<<4)
     OUTMODE_OUTOFF = (1<<3)
-    OUTMODE_2L_16B = (0<<0)
-    OUTMODE_2L_14B = (1<<0)
-    OUTMODE_2L_12B = (2<<0)
-    OUTMODE_1L_14B = (5<<0)
-    OUTMODE_1L_12B = (6<<0)
-    OUTMODE_1L_16B = (7<<0)
+    OUTMODE_MASK = 0x07
 
     TESTPAT_MSB_OUTTEST = (1<<7)
     TESTPAT_MSB_MASK = 0x3F
     TESTPAT_LSB_MASK = 0xFF
 
+    # Constant definitions
+    ILVDS = {'3.5mA':0x0, '4.0mA':0x1, '4.5mA':0x2, '3.0mA':0x4, '2.5mA':0x5, '2.1mA':0x6, '1.75mA':0x7}
+    OUTMODE = {'2lanes16bit':0x0, '2lanes14bit':0x1, '2lanes12bit':0x2, '1lane14bit':0x5, '1lane12bit':0x6, '1lane16bit':0x7}
+
     # addr = ltc217x register address (1 byte)
     # value = value to write to the register (1 byte)
     def wr_reg(self, addr, value):
         tx = [value, addr]
         self.spi.transaction(self.slave, tx)
 
+    # addr = ltc217x register address (1 byte)
+    # return = value of the register (1 byte)
     def rd_reg(self, addr):
         tx = [0xFF, (addr | 0x80)]
         rx = self.spi.transaction(self.slave, tx)
@@ -59,18 +68,76 @@ class CLTC217x:
         self.spi = spi
         self.slave = slave
         self.wr_reg(self.R_RST, self.RST)
-        #self.wr_reg(self.R_FMT, 0)
         self.wr_reg(self.R_FMT, self.FMT_TWOSCOMP)
+        self.wr_reg(self.R_OUTMODE, (self.OUTMODE_ILVDS_4M5 | self.OUTMODE_2L_16B))
+        #self.wr_reg(self.R_FMT, 0)
         #self.wr_reg(self.R_OUTMODE, (self.OUTMODE_ILVDS_4M5 | self.OUTMODE_2L_16B | self.OUTMODE_TERMON))
         #self.wr_reg(self.R_OUTMODE, (self.OUTMODE_ILVDS_2M5 | self.OUTMODE_2L_16B | self.OUTMODE_TERMON))
-        self.wr_reg(self.R_OUTMODE, (self.OUTMODE_ILVDS_4M5 | self.OUTMODE_2L_16B))
+
+    def reset(self):
+        self.wr_reg(self.R_RST, self.RST)
 
     def get_fmt(self):
         return self.rd_reg(self.R_FMT)
 
+    def set_fmt(self, value):
+        self.wr_reg(self.R_FMT, value)
+        return self.rd_reg(self.R_FMT)
+
+    def channel_nap(self, ch, en):
+        reg = self.rd_reg(self.R_FMT)
+        if(en):
+            reg |= (1 << (ch-1))
+        else:
+            reg &= ~(1 << (ch-1))
+        self.wr_reg(self.R_FMT, reg)
+
+    def sleep(self, en):
+        reg = self.rd_reg(self.R_FMT)
+        if(en):
+            reg |= self.FMT_SLEEP
+        else:
+            reg &= ~(self.FMT_SLEEP)
+        self.wr_reg(self.R_FMT, reg)
+
+    def twos_complement(self, en):
+        reg = self.rd_reg(self.R_FMT)
+        if(en):
+            # enable tow's complement data output format
+            reg |= self.FMT_TOWSCOMP
+        else:
+            # binary offset data output format
+            reg &= ~(self.FMT_TOWSCOMP)
+        self.wr_reg(self.R_FMT, reg)
+
+    def random(self, en):
+        reg = self.rd_reg(self.R_FMT)
+        if(en):
+            # Enable random data output
+            reg |= self.FMT_RAND
+        else:
+            # Disable random data output
+            reg &= ~(self.FMT_RAND)
+        self.wr_reg(self.R_FMT, reg)
+
+    def duty_cycle_stabiliser_dis(self, dis):
+        reg = self.rd_reg(self.R_FMT)
+        if(dis):
+            reg |= self.FMT_DCSOFF
+        else:
+            reg &= ~(self.FMT_DCSOFF)
+        self.wr_reg(self.R_FMT, reg)
+
     def get_outmode(self):
         return self.rd_reg(self.R_OUTMODE)
 
+    def set_outmode(self, value):
+        self.wr_reg(self.R_OUTMODE, value)
+        return self.rd_reg(self.R_OUTMODE)
+
+    def set_i_lvds(self, current):
+        
+
     def get_testpat(self):
         return (((self.rd_reg(self.R_TESTPAT_MSB) & self.TESTPAT_MSB_MASK)<<8)
                 + (self.rd_reg(self.R_TESTPAT_LSB) & self.TESTPAT_LSB_MASK))

common/spi.py

-#!/usr/bin/python
+#!   /usr/bin/env   python
+#    coding: utf8
 
 # Copyright CERN, 2011
 # Author: Matthieu Cattin (CERN)
@@ -23,9 +24,8 @@ class SPIDeviceOperationError(Exception):
         return ("SPI Device produced the error: %s" %(msg))
 
 class COpenCoresSPI:
-
         # OpenCores SPI registers description
-	R_RX = [0x00, 0x04, 0x08, 0x0C]
+        R_RX = [0x00, 0x04, 0x08, 0x0C]
 	R_TX = [0x00, 0x04, 0x08, 0x0C]
 	R_CTRL = 0x10
 	R_DIV = 0x14