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misc
pts-base
Commits
3cd3f4a2
Commit
3cd3f4a2
authored
12 years ago
by
Matthieu Cattin
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common:gn4124: Fix bug in wait interrupt. Was not re-enabling interrupt after handling it.
Add a function to read gn4124 interrupt configuration.
parent
988ffd32
No related merge requests found
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common/gn4124.py
+19
-2
19 additions, 2 deletions
common/gn4124.py
with
19 additions
and
2 deletions
common/gn4124.py
+
19
−
2
View file @
3cd3f4a2
...
...
@@ -42,9 +42,11 @@ class CGN4124:
R_CLK_CSR
=
0x808
R_INT_CFG0
=
0x820
R_GPIO_DIR_MODE
=
0xA04
R_GPIO_INT_MASK
=
0xA14
R_GPIO_INT_MASK_CLR
=
0xA18
R_GPIO_INT_MASK_SET
=
0xA1C
R_GPIO_INT_STATUS
=
0xA20
R_GPIO_INT_TYPE
=
0xA24
R_GPIO_INT_VALUE
=
0xA28
CLK_CSR_DIVOT_MASK
=
0x3F0
...
...
@@ -121,8 +123,13 @@ class CGN4124:
self
.
bus
.
irqena
()
# Wait for interrupt
def
wait_irq
(
self
):
return
self
.
bus
.
irqwait
()
def
wait_irq
(
self
,
verbose
=
False
):
if
verbose
:
print
(
"
[GN4124] Waiting IRQ...
"
)
ret
=
self
.
bus
.
irqwait
()
# re-enable the interrupt
self
.
bus
.
irqena
()
return
ret
# GN4124 RSTOUT33 assert/de-assert cycle
def
rstout33_cycle
(
self
):
...
...
@@ -139,11 +146,21 @@ class CGN4124:
self
.
wr_reg
(
self
.
GN4124_BAR
,
self
.
R_GPIO_INT_MASK_SET
,
~
(
1
<<
self
.
GPIO_INT_SRC
))
# Make sure the interrupt mask is cleared for GPIO8
self
.
wr_reg
(
self
.
GN4124_BAR
,
self
.
R_GPIO_INT_MASK_CLR
,
(
1
<<
self
.
GPIO_INT_SRC
))
# Make sure the interrupt is edge sensitive for GPIO8
self
.
wr_reg
(
self
.
GN4124_BAR
,
self
.
R_GPIO_INT_TYPE
,
0x0
)
# Interrupt on rising edge of GPIO8
self
.
wr_reg
(
self
.
GN4124_BAR
,
self
.
R_GPIO_INT_VALUE
,
(
1
<<
self
.
GPIO_INT_SRC
))
# GPIO as interrupt 0 source
self
.
wr_reg
(
self
.
GN4124_BAR
,
self
.
R_INT_CFG0
,
(
1
<<
self
.
INT_CFG0_GPIO
))
def
get_interrupt_config
(
self
):
dir_mode
=
self
.
rd_reg
(
self
.
GN4124_BAR
,
self
.
R_GPIO_DIR_MODE
)
int_mask
=
self
.
rd_reg
(
self
.
GN4124_BAR
,
self
.
R_GPIO_INT_MASK
)
int_type
=
self
.
rd_reg
(
self
.
GN4124_BAR
,
self
.
R_GPIO_INT_TYPE
)
int_value
=
self
.
rd_reg
(
self
.
GN4124_BAR
,
self
.
R_GPIO_INT_VALUE
)
int_cfg
=
self
.
rd_reg
(
self
.
GN4124_BAR
,
self
.
R_INT_CFG0
)
return
dir_mode
,
int_mask
,
int_type
,
int_value
,
int_cfg
# Get DMA controller status
def
get_dma_status
(
self
):
reg
=
self
.
dma_csr
.
rd_reg
(
self
.
R_DMA_STA
)
...
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