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Platform-independent core collection
Commit cd6752e6 authored by CI's avatar CI
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Simple cleanup and README added

parent cf1946c6
Pipeline #3609 passed with stage
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    Showing with 138 additions and 139 deletions
    testbench/common/gc_fsm_watchdog/work-obj08.cf deleted 100644 → 0
    View file @ cf1946c6
    v 4
    file . "tb_gc_fsm_watchdog.vhd" "ef4a9560706526d39751607434cbe294402664ed" "20220425130705.096":
    entity tb_gc_fsm_watchdog at 30( 1360) + 0 on 23;
    architecture tb of tb_gc_fsm_watchdog at 47( 1658) + 0 on 24;
    file . "../../../modules/common/gencores_pkg.vhd" "b36dddafc7e103fcd1c62bdc4888bcd06718a06f" "20220425130417.306":
    package gencores_pkg at 26( 1281) + 0 on 11 body;
    package body gencores_pkg at 792( 29734) + 0 on 12;
    file . "../../../modules/common/gc_fsm_watchdog.vhd" "591631d15e14c9ef96be25b94d63b6ff810dde41" "20220425130417.321":
    entity gc_fsm_watchdog at 37( 1584) + 0 on 13;
    architecture behav of gc_fsm_watchdog at 64( 2147) + 0 on 14;
    testbench/common/gc_fsm_watchdog/Makefile → testbench/common/gc_sync/Makefile
    View file @ cd6752e6
    ......@@ -3,7 +3,7 @@
    # http://ohwr.org/projects/hdl-make/ #
    ########################################
    TOP_MODULE := tb_gc_fsm_watchdog
    TOP_MODULE := tb_gc_sync
    GHDL := ghdl
    GHDL_OPT := --std=08 -frelaxed-rules
    ......@@ -13,13 +13,11 @@ local: sim_pre_cmd simulation sim_post_cmd
    VERILOG_SRC :=
    VERILOG_OBJ :=
    VHDL_SRC := ../../../modules/common/gc_fsm_watchdog.vhd \
    ../../../modules/common/gencores_pkg.vhd \
    tb_gc_fsm_watchdog.vhd \
    VHDL_SRC := ../../../modules/common/gc_sync.vhd \
    tb_gc_sync.vhd \
    VHDL_OBJ := work/gc_fsm_watchdog/.gc_fsm_watchdog_vhd \
    work/gencores_pkg/.gencores_pkg_vhd \
    work/tb_gc_fsm_watchdog/.tb_gc_fsm_watchdog_vhd \
    VHDL_OBJ := work/gc_sync/.gc_sync_vhd \
    work/tb_gc_sync/.tb_gc_sync_vhd \
    LIBS := work
    LIB_IND := work/.work
    ......@@ -28,20 +26,13 @@ simulation: $(VERILOG_OBJ) $(VHDL_OBJ)
    $(GHDL) -e $(GHDL_OPT) $(TOP_MODULE)
    work/gc_fsm_watchdog/.gc_fsm_watchdog_vhd: ../../../modules/common/gc_fsm_watchdog.vhd \
    work/gencores_pkg/.gencores_pkg_vhd
    work/gc_sync/.gc_sync_vhd: ../../../modules/common/gc_sync.vhd
    $(GHDL) -a --work=work $(GHDL_OPT) $<
    @mkdir -p $(dir $@) && touch $@
    work/gencores_pkg/.gencores_pkg_vhd: ../../../modules/common/gencores_pkg.vhd
    $(GHDL) -a --work=work $(GHDL_OPT) $<
    @mkdir -p $(dir $@) && touch $@
    work/tb_gc_fsm_watchdog/.tb_gc_fsm_watchdog_vhd: tb_gc_fsm_watchdog.vhd \
    work/gc_fsm_watchdog/.gc_fsm_watchdog_vhd \
    work/gencores_pkg/.gencores_pkg_vhd
    work/tb_gc_sync/.tb_gc_sync_vhd: tb_gc_sync.vhd \
    work/gc_sync/.gc_sync_vhd
    $(GHDL) -a --work=work $(GHDL_OPT) $<
    @mkdir -p $(dir $@) && touch $@
    ......
    testbench/common/gc_sync/README.md 0 → 100644
    View file @ cd6752e6
    Testbench to verify the functionality of gc_sync general core. It uses GHDL simulator and OSVVM verification methodology. Through the `g_sync_edge` there is an option of working for positive or negative clock edge. Due to that, there can be two test cases. The value of the input signal, is random with random seed in every run. This can be achieved from OSVVM methodology as well.
    One assertion exist in the testbench in order to provide a more self-checking approach. It checks if the output is asserted (or de-asserted in falling edge of the clock), after 2 clock cycles.
    testbench/common/gc_fsm_watchdog/osvvm/v08/osvvm-obj08.cf → testbench/common/gc_sync/osvvm/v08/osvvm-obj08.cf
    View file @ cd6752e6
    v 4
    file / "/home/kostas/projects/OSVVM-2020.05/./OsvvmContext.vhd" "7caf9c820caaaf1cb4076e945f29b69fdc322cb7" "20220425130411.752":
    file / "/home/kostas/projects/OSVVM-2020.05/./OsvvmContext.vhd" "7caf9c820caaaf1cb4076e945f29b69fdc322cb7" "20220429092245.072":
    context osvvmcontext at 42( 1383) + 0 on 43;
    file / "/home/kostas/projects/OSVVM-2020.05/./ResolutionPkg.vhd" "7f9a11e2a368d9be844525a6b89854f2cf4ff051" "20220425130411.707":
    file / "/home/kostas/projects/OSVVM-2020.05/./ResolutionPkg.vhd" "7f9a11e2a368d9be844525a6b89854f2cf4ff051" "20220429092245.027":
    package resolutionpkg at 50( 1945) + 0 on 39 body;
    package body resolutionpkg at 181( 8649) + 0 on 40;
    file / "/home/kostas/projects/OSVVM-2020.05/./ScoreboardPkg_slv.vhd" "d3c3c2c79c8650d22557261042f3e22f3e266204" "20220425130411.667":
    file / "/home/kostas/projects/OSVVM-2020.05/./ScoreboardPkg_slv.vhd" "d3c3c2c79c8650d22557261042f3e22f3e266204" "20220429092244.987":
    package scoreboardpkg_slv at 46( 1539) + 0 on 37;
    file / "/home/kostas/projects/OSVVM-2020.05/./MemoryPkg.vhd" "8d9c06f35f468990d74f54153afbca1078814fdb" "20220425130411.623":
    file / "/home/kostas/projects/OSVVM-2020.05/./MemoryPkg.vhd" "8d9c06f35f468990d74f54153afbca1078814fdb" "20220429092244.943":
    package memorypkg at 47( 1725) + 0 on 33 body;
    package body memorypkg at 122( 4496) + 0 on 34;
    file / "/home/kostas/projects/OSVVM-2020.05/./RandomPkg.vhd" "cfa3c4f16f324b3f487449ab037f05051542384c" "20220425130411.557":
    file / "/home/kostas/projects/OSVVM-2020.05/./RandomPkg.vhd" "cfa3c4f16f324b3f487449ab037f05051542384c" "20220429092244.876":
    package randompkg at 70( 3318) + 0 on 29 body;
    package body randompkg at 321( 17467) + 0 on 30;
    file / "/home/kostas/projects/OSVVM-2020.05/./SortListPkg_int.vhd" "42412d6fa3019a40d8fb1bf8c5fae04f993e543b" "20220425130411.518":
    file / "/home/kostas/projects/OSVVM-2020.05/./SortListPkg_int.vhd" "42412d6fa3019a40d8fb1bf8c5fae04f993e543b" "20220429092244.834":
    package sortlistpkg_int at 56( 2308) + 0 on 25 body;
    package body sortlistpkg_int at 110( 4750) + 0 on 26;
    file / "/home/kostas/projects/OSVVM-2020.05/./AlertLogPkg.vhd" "5278ba6c53809cb49a15f10ed3ff27278a4bbdce" "20220425130411.486":
    file / "/home/kostas/projects/OSVVM-2020.05/./AlertLogPkg.vhd" "5278ba6c53809cb49a15f10ed3ff27278a4bbdce" "20220429092244.803":
    package alertlogpkg at 74( 3773) + 0 on 21 body;
    package body alertlogpkg at 452( 29877) + 0 on 22;
    file / "/home/kostas/projects/OSVVM-2020.05/./TranscriptPkg.vhd" "be05f359f79b58ab93b24b6b8c4465e68a191d6d" "20220425130411.441":
    file / "/home/kostas/projects/OSVVM-2020.05/./TranscriptPkg.vhd" "be05f359f79b58ab93b24b6b8c4465e68a191d6d" "20220429092244.731":
    package transcriptpkg at 47( 1549) + 0 on 17 body;
    package body transcriptpkg at 83( 3339) + 0 on 18;
    file / "/home/kostas/projects/OSVVM-2020.05/./OsvvmGlobalPkg.vhd" "f39a10e4df2d56924d1b4c102fa30056434233de" "20220425130411.431":
    file / "/home/kostas/projects/OSVVM-2020.05/./OsvvmGlobalPkg.vhd" "f39a10e4df2d56924d1b4c102fa30056434233de" "20220429092244.706":
    package osvvmglobalpkg at 44( 1357) + 0 on 13 body;
    package body osvvmglobalpkg at 122( 5395) + 0 on 14;
    file / "/home/kostas/projects/OSVVM-2020.05/./NamePkg.vhd" "b1c254782f50b1a6b6cd385d57e270afbb3803c6" "20220425130411.423":
    file / "/home/kostas/projects/OSVVM-2020.05/./NamePkg.vhd" "b1c254782f50b1a6b6cd385d57e270afbb3803c6" "20220429092244.684":
    package namepkg at 47( 1653) + 0 on 11 body;
    package body namepkg at 66( 2310) + 0 on 12;
    file / "/home/kostas/projects/OSVVM-2020.05/./VendorCovApiPkg.vhd" "8cd4cddbc58ffc88984c844facbb9fc6bca24393" "20220425130411.435":
    file / "/home/kostas/projects/OSVVM-2020.05/./VendorCovApiPkg.vhd" "8cd4cddbc58ffc88984c844facbb9fc6bca24393" "20220429092244.716":
    package vendorcovapipkg at 42( 1371) + 0 on 15 body;
    package body vendorcovapipkg at 81( 3215) + 0 on 16;
    file / "/home/kostas/projects/OSVVM-2020.05/./TextUtilPkg.vhd" "2d48fa4dac4d4f5f1b1f41d5aff41f7580803a17" "20220425130411.449":
    file / "/home/kostas/projects/OSVVM-2020.05/./TextUtilPkg.vhd" "2d48fa4dac4d4f5f1b1f41d5aff41f7580803a17" "20220429092244.750":
    package textutilpkg at 46( 1470) + 0 on 19 body;
    package body textutilpkg at 106( 3864) + 0 on 20;
    file / "/home/kostas/projects/OSVVM-2020.05/./MessagePkg.vhd" "5d00b08ecfd2d623922fa3f93c997ea9793e32e5" "20220425130411.502":
    file / "/home/kostas/projects/OSVVM-2020.05/./MessagePkg.vhd" "5d00b08ecfd2d623922fa3f93c997ea9793e32e5" "20220429092244.819":
    package messagepkg at 46( 1734) + 0 on 23 body;
    package body messagepkg at 74( 2572) + 0 on 24;
    file / "/home/kostas/projects/OSVVM-2020.05/./RandomBasePkg.vhd" "060fedb6bb8af5bdb8a4f0b720c6c5f9c4e76537" "20220425130411.532":
    file / "/home/kostas/projects/OSVVM-2020.05/./RandomBasePkg.vhd" "060fedb6bb8af5bdb8a4f0b720c6c5f9c4e76537" "20220429092244.849":
    package randombasepkg at 63( 2472) + 0 on 27 body;
    package body randombasepkg at 104( 4238) + 0 on 28;
    file / "/home/kostas/projects/OSVVM-2020.05/./CoveragePkg.vhd" "a757b2d58776adaf1f4aafdce5fa8edde2992997" "20220425130411.603":
    file / "/home/kostas/projects/OSVVM-2020.05/./CoveragePkg.vhd" "a757b2d58776adaf1f4aafdce5fa8edde2992997" "20220429092244.923":
    package coveragepkg at 89( 4929) + 0 on 31 body;
    package body coveragepkg at 807( 39309) + 0 on 32;
    file / "/home/kostas/projects/OSVVM-2020.05/./ScoreboardGenericPkg.vhd" "b4c48bc792b46dec46f030f4855dbdfc23e972c8" "20220425130411.643":
    file / "/home/kostas/projects/OSVVM-2020.05/./ScoreboardGenericPkg.vhd" "b4c48bc792b46dec46f030f4855dbdfc23e972c8" "20220429092244.963":
    package scoreboardgenericpkg at 64( 2836) + 0 on 35 body;
    package body scoreboardgenericpkg at 458( 19357) + 0 on 36;
    file / "/home/kostas/projects/OSVVM-2020.05/./ScoreboardPkg_int.vhd" "34b35f7e1ee1534cca83d070d00459118bc04b1f" "20220425130411.691":
    file / "/home/kostas/projects/OSVVM-2020.05/./ScoreboardPkg_int.vhd" "34b35f7e1ee1534cca83d070d00459118bc04b1f" "20220429092245.011":
    package scoreboardpkg_int at 45( 1529) + 0 on 38;
    file / "/home/kostas/projects/OSVVM-2020.05/./TbUtilPkg.vhd" "70d8481b7452ebc8435b7c151f1902543558a5e9" "20220425130411.723":
    file / "/home/kostas/projects/OSVVM-2020.05/./TbUtilPkg.vhd" "70d8481b7452ebc8435b7c151f1902543558a5e9" "20220429092245.044":
    package tbutilpkg at 48( 1869) + 0 on 41 body;
    package body tbutilpkg at 275( 11277) + 0 on 42;
    testbench/common/gc_sync/run.sh
    View file @ cd6752e6
    ......@@ -6,11 +6,13 @@ TB=tb_gc_sync
    echo "Running simulation for $TB"
    echo " TEST CASE 1 "
    echo "SYNC_EDGE=positive"
    ghdl -r --std=08 -frelaxed-rules $TB -gg_SYNC_EDGE=positive --vcd=waveform.vcd
    ghdl -r --std=08 -frelaxed-rules $TB -gg_seed=$RANDOM -gg_SYNC_EDGE=positive
    echo "**********************************************************************"
    echo " TEST CASE 2 "
    echo "SYNC_EDGE=negative"
    ghdl -r --std=08 -frelaxed-rules $TB -gg_SYNC_EDGE=negative --vcd=waveform.vcd
    ghdl -r --std=08 -frelaxed-rules $TB -gg_seed=$RANDOM -gg_SYNC_EDGE=negative
    echo "**********************************************************************"
    #Printing result
    echo "Test PASS"
    testbench/common/gc_sync/tb_gc_sync.vhd
    View file @ cd6752e6
    ......@@ -28,122 +28,126 @@ library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    -- OSVVM library
    library osvvm;
    use osvvm.RandomPkg.all;
    use osvvm.CoveragePkg.all;
    entity tb_gc_sync is
    generic (
    g_SYNC_EDGE : string := "positive");
    generic (
    g_seed : natural;
    g_SYNC_EDGE : string := "positive");
    end entity;
    architecture tb of tb_gc_sync is
    --constants
    -- Constants
    constant C_CLK_PERIOD : time := 10 ns;
    --signal declaration
    -- Signals
    signal tb_clk_i : std_logic;
    signal tb_rst_i : std_logic;
    signal tb_d_i : std_logic := '0';
    signal tb_q_o : std_logic;
    signal stop : boolean;
    shared variable cp_rst_i : covPType;
    -- Shared variables, used for coverage
    shared variable cp_rst_i : covPType;
    signal Stop : BOOLEAN;
    begin
    --Unit Under Test
    --Unit Under Test
    UUT : entity work.gc_sync
    generic map (
    g_SYNC_EDGE => g_SYNC_EDGE)
    port map (
    clk_i => tb_clk_i,
    clk_i => tb_clk_i,
    rst_n_a_i => tb_rst_i,
    d_i => tb_d_i,
    q_o => tb_q_o);
    --Clock generation
    clk_i_process : process
    begin
    while STOP = FALSE loop
    tb_clk_i <= '0';
    wait for C_CLK_PERIOD/2;
    tb_clk_i <= '1';
    wait for C_CLK_PERIOD/2;
    end loop;
    wait;
    end process;
    tb_rst_i <= '0', '1' after 2*C_CLK_PERIOD;
    -- Randomized stimulus
    Stim: process
    -- The random variables
    variable data_i : RandomPType;
    -- ncycles counts how many vectors were applied
    variable ncycles : natural;
    begin
    -- NOW < 1ms is a timeout in case no error occured
    while (NOW < 1 ms) loop
    wait until (rising_edge(tb_clk_i));
    tb_d_i <= data_i.RandSlv(1)(1);
    nCycles := nCycles + 1;
    end loop;
    report "Number of simulation cycles = " & to_string(nCycles);
    STOP <= TRUE;
    wait;
    end process Stim;
    --sets up coverpoint bins
    InitCoverage: process
    begin
    cp_rst_i.AddBins("reset has asserted", ONE_BIN);
    wait;
    end process InitCoverage;
    -- Always checking the delay of the output to be 2 clock cycles
    check_output : process
    begin
    if (rising_edge(tb_clk_i)) then
    if (tb_d_i = '1') then
    wait for 2*C_CLK_PERIOD;
    assert (tb_q_o = '1')
    report "output not asserted after two clocks" severity failure;
    else
    wait for 2*C_CLK_PERIOD;
    assert (tb_q_o = '0')
    report "output not de-asserted after two clocks" severity failure;
    end if;
    end if;
    wait;
    end process;
    Sample: process
    begin
    loop
    wait on tb_rst_i;
    -- Sample the simple coverpoints
    cp_rst_i.ICover (to_integer(tb_rst_i = '1'));
    end loop;
    end process Sample;
    CoverReport: process
    begin
    wait until STOP;
    report "reset asserted";
    cp_rst_i.writebin;
    report "PASS";
    end process;
    --Clock generation
    clk_i_process : process
    begin
    while not stop loop
    tb_clk_i <= '0';
    wait for C_CLK_PERIOD/2;
    tb_clk_i <= '1';
    wait for C_CLK_PERIOD/2;
    end loop;
    wait;
    end process;
    -- Reset generation
    tb_rst_i <= '0', '1' after 2*C_CLK_PERIOD;
    -- Randomized stimulus
    Stim: process
    variable data : RandomPType;
    variable ncycles : natural;
    begin
    data.InitSeed(g_seed);
    report "[STARTING] with seed = " & to_string(g_seed);
    while NOW < 2 ms loop
    wait until rising_edge(tb_clk_i);
    tb_d_i <= data.RandSlv(1)(1);
    nCycles := nCycles + 1;
    end loop;
    report "Number of simulation cycles = " & to_string(nCycles);
    STOP <= TRUE;
    report "Test PASS";
    wait;
    end process Stim;
    -------------------------------------------------------------------------------
    -- Assertions --
    -------------------------------------------------------------------------------
    -- Always checking the delay of the output to be 2 clock cycles
    check_output : process
    begin
    if rising_edge(tb_clk_i) then
    if tb_d_i = '1' then
    wait for 2*C_CLK_PERIOD;
    assert (tb_q_o = '1')
    report "output not asserted after two clocks" severity failure;
    else
    wait for 2*C_CLK_PERIOD;
    assert (tb_q_o = '0')
    report "output not de-asserted after two clocks" severity failure;
    end if;
    end if;
    wait;
    end process;
    -------------------------------------------------------------------------------
    -- Coverage --
    -------------------------------------------------------------------------------
    --sets up coverpoint bins
    InitCoverage: process
    begin
    cp_rst_i.AddBins("reset has asserted", ONE_BIN);
    wait;
    end process InitCoverage;
    Sample: process
    begin
    loop
    wait on tb_rst_i;
    cp_rst_i.ICover (to_integer(tb_rst_i = '1'));
    end loop;
    end process Sample;
    CoverReport: process
    begin
    wait until STOP;
    cp_rst_i.writebin;
    report "PASS";
    end process;
    end tb;
    testbench/common/gc_sync/work-obj08.cf 0 → 100644
    View file @ cd6752e6
    v 4
    file . "tb_gc_sync.vhd" "e9f23acd59012907e4a52aa38abf4220148e5a73" "20220429092250.097":
    entity tb_gc_sync at 27( 1320) + 0 on 13;
    architecture tb of tb_gc_sync at 44( 1590) + 0 on 14;
    file . "../../../modules/common/gc_sync.vhd" "57c932a395ae780b2f36fc65143fd10d40a50172" "20220429092250.050":
    entity gc_sync at 25( 1235) + 0 on 11;
    architecture arch of gc_sync at 42( 1635) + 0 on 12;
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