This is a testbench to verify the gc_dual_pi_controler core. It uses GHDL simulator and OSVVM as verification methodology. All input signals in the testbench are random, with random seed also. There are two generics in the core:
- g_div_ratio_log2 : Clock division ratio
- g_num_data_bits : Number of data bits per transfer
Regarding the assigned values in these generic, there can be various combinations (testcases), some of them are presented here (1,1), (2,2), (2,4), (3,4).
The testbench, receives random input data (with random seeds). A clock divider counter generates s_tick which is used to control the FSM. One assertion exist in the testbench to bring self-checking capabilities in it and checks, if the incoming data is equal with the outcoming data, in the end of the FSM process.
FSM coverage is covered through the use of OSVVM methodology, where the transition of the states is being checked in every clock and the reports are shown in the end.
Testbench to verify the functionality of the gc_single_reset_gen general core. It uses GHDL simulator and OSVVM verification methodology. This core is having 2 generics in the entity:
- g_out_reg_depth : Number of Flip-Flos before the signal's output
- g_rst_in_num : Number of input async reset signals
The testcases of the testbench can arise from a combination of these generics. There can be many testcases, but in here there are tested the following: (1,1), (2,2), (4,5), (2,8).
The testing process is very simple. It receives random input data (with random seeds). It uses a similar logic to the one that RTL uses and generates a testbench output. Some assertions exist in the testbench to bring self-checking capabilities in it, which are:
- Check that the number of f/f before the final signals' output is valid
- Check that number of asynchronous reset signals is valid
- Compare the output reset of testbench to be the same as the one from RTL core
- Reset to not be asserted before the powerup
Simple coverage is being covered also:
- Powerup has done (at least 1 time per simulation)
