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Konstantinos Blantos
Platform-independent core collection
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feature/wb_spi-sim
d93f29f4
·
[hdl] WIP to introduce a testbench for the WB SPI master.
·
Mar 30, 2020
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pascal_axi
bbc00bce
·
fixed sel stuck at zero when reading
·
Apr 01, 2020
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cleanup_includes
c88b075f
·
Remove unnecessary includes.
·
Apr 07, 2020
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btrain-v1.2
c0e85653
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[hdl] add missing generic to generic_dpram in altera
·
Apr 09, 2020
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tom-fine-pulse-gen-apr01
08d07c21
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wb_fine_pulse_gen: use double clock rate on Kintex7 Ultrascale, allowing for 1ns resolution
·
Apr 16, 2020
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wb_axi_bridge_fixes
496eced5
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Fix BVALID signalling in AXI4Lite-to-WB bridge wrapper
·
Apr 30, 2020
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tom-may13
273418d4
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gc_simple_spi_master: keep MOSI at 0 when inactive so that multi-master SPI...
·
May 13, 2020
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tom-proposed-master-jun30
dd281822
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sim/if_wb_master: return accessor object as a singleton
·
Jul 01, 2020
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proposed_spec7
a53c3b85
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fixed reading issue occuring when stall and ack are changing at the same time
·
Jul 03, 2020
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ML-new_wrs-4_resource_eval
282fa737
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trivial fix
·
Jul 09, 2020
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peter_proposed_spec7_v5
560dea33
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fixed reading issue occuring when stall and ack are changing at the same time
·
Jul 16, 2020
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tom-jun30
e1143c36
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wb_fine_pulse_gen: simplify clock crossings
·
Jul 17, 2020
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tom-sis83k-aug25
e1143c36
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wb_fine_pulse_gen: simplify clock crossings
·
Jul 17, 2020
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tom-afcz-aug25
6e683cb6
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gc_simple_spi_master: keep MOSI at 0 when inactive so that multi-master SPI...
·
Aug 06, 2020
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tom-10g-hacks
f30e69b9
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xwb_axi4lite_bridge: correctly resolve bursts
·
Aug 14, 2020
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for-simulated-hw
f040025f
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sdb_crossbar: write sdb-tables into C header files
·
Aug 26, 2020
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tom-ertm14
91bbf080
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wishbone: UART now supports configurable FIFOs
·
Aug 27, 2020
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gsi_master_get_back_on_track_aug_2020
65f4fe8e
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Fixed UARTs too short delay between RX read and ACK
·
Sep 15, 2020
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pascal_201006
7498609f
·
renamed pci to pcie, moved to bd format
·
Oct 07, 2020
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peter_201007
012b58c6
·
added processing_system_pcie.bd
·
Oct 07, 2020
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