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Konstantinos Blantos
Platform-independent core collection
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bc6bcba1
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Change in Makefile. Now in every single error, the CI will stop
·
Sep 06, 2022
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proposed_master
7d76d2b6
·
Merge branch 'add_scoped_xdc' into 'proposed_master'
·
Oct 01, 2021
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develop
16b7b936
·
Merge tag 'v1.1.2' into develop
·
Jul 29, 2021
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tom-rf
dfdb1574
·
wb_fine_pulse_gen: support for configurable pulse width. INTERFACE CHANGED.
·
May 11, 2021
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vivado-2019.2
b75fe3d5
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gc_frequency_meter: DO NOT MERGE, temporary fix to make buggy vivado hierarchy solver happy
·
May 06, 2021
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sync_reset_state
cb09c893
·
Add configurable reset state for sync/edge_detect IP
·
Apr 15, 2021
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tom-rf-mar11
c68481b6
·
wb_uart: temporary fix for eRTM UART FIFO issue causing RX data loss. VUART...
·
Mar 11, 2021
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gsi_master_get_back_on_track
99d1fa3e
·
pcie_altera: added pex10 and ftm10 instantiation
·
Feb 17, 2021
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peter_210106_spec7
55d2e8cc
·
added processing_system_pcie.bd
·
Jan 06, 2021
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tom-dec11
ed011735
·
wb_xc7_fw_update: keep STARTUP primitive outside the core
·
Dec 11, 2020
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peter_201007
012b58c6
·
added processing_system_pcie.bd
·
Oct 07, 2020
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pascal_201006
7498609f
·
renamed pci to pcie, moved to bd format
·
Oct 07, 2020
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gsi_master_get_back_on_track_aug_2020
65f4fe8e
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Fixed UARTs too short delay between RX read and ACK
·
Sep 15, 2020
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tom-ertm14
91bbf080
·
wishbone: UART now supports configurable FIFOs
·
Aug 27, 2020
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for-simulated-hw
f040025f
·
sdb_crossbar: write sdb-tables into C header files
·
Aug 26, 2020
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tom-10g-hacks
f30e69b9
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xwb_axi4lite_bridge: correctly resolve bursts
·
Aug 14, 2020
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tom-afcz-aug25
6e683cb6
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gc_simple_spi_master: keep MOSI at 0 when inactive so that multi-master SPI...
·
Aug 06, 2020
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tom-jun30
e1143c36
·
wb_fine_pulse_gen: simplify clock crossings
·
Jul 17, 2020
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tom-sis83k-aug25
e1143c36
·
wb_fine_pulse_gen: simplify clock crossings
·
Jul 17, 2020
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peter_proposed_spec7_v5
560dea33
·
fixed reading issue occuring when stall and ack are changing at the same time
·
Jul 16, 2020
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