Skip to content

U
urv-core
Commit ded49985 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

updated copyright notice

parent 2c1d6de5
Hide whitespace changes
Inline Side-by-side
Showing with 5 additions and 6 deletions
syn/spec/spec_top.bmm
View file @ ded49985
ADDRESS_SPACE urv_iram RAMB16 [0x00000000:0x000FFFF] ADDRESS_SPACE urv_iram RAMB16 [0x00000000:0x000fFFF]
BUS_BLOCK BUS_BLOCK
U_CPU/U_iram/RV_IRAM_BLK_64K_31 [31]; U_CPU/U_iram/RV_IRAM_BLK_64K_31 [31];
U_CPU/U_iram/RV_IRAM_BLK_64K_30 [30]; U_CPU/U_iram/RV_IRAM_BLK_64K_30 [30];
......
top/spec/spec_top.vhd
View file @ ded49985
-- --
-- DSI Shield -- uRV - a tiny and dumb RISC-V core
-- Copyright (C) 2013-2014 twl <twlostow@printf.cc> -- Copyright (c) 2015 CERN
-- -- Author: Tomasz Włostowski <tomasz.wlostowski@cern.ch>
-- This library is free software; you can redistribute it and/or -- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public -- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either -- License as published by the Free Software Foundation; either
...@@ -31,8 +32,6 @@ use work.wishbone_pkg.all; ...@@ -31,8 +32,6 @@ use work.wishbone_pkg.all;
library unisim; library unisim;
use unisim.vcomponents.all; use unisim.vcomponents.all;
entity spec_top is entity spec_top is
generic ( generic (
g_riscv_firmware : string := "uart-bootloader.ram"; g_riscv_firmware : string := "uart-bootloader.ram";
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment