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hdl-core-lib
urv-core
Commits
ded49985
Commit
ded49985
authored
Oct 09, 2015
by
Tomasz Wlostowski
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updated copyright notice
parent
2c1d6de5
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6 deletions
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-6
spec_top.bmm
syn/spec/spec_top.bmm
+1
-1
spec_top.vhd
top/spec/spec_top.vhd
+4
-5
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syn/spec/spec_top.bmm
View file @
ded49985
ADDRESS_SPACE urv_iram RAMB16 [0x00000000:0x000
F
FFF]
ADDRESS_SPACE urv_iram RAMB16 [0x00000000:0x000
f
FFF]
BUS_BLOCK
U_CPU/U_iram/RV_IRAM_BLK_64K_31 [31];
U_CPU/U_iram/RV_IRAM_BLK_64K_30 [30];
...
...
top/spec/spec_top.vhd
View file @
ded49985
--
-- DSI Shield
-- Copyright (C) 2013-2014 twl <twlostow@printf.cc>
--
-- uRV - a tiny and dumb RISC-V core
-- Copyright (c) 2015 CERN
-- Author: Tomasz Włostowski <tomasz.wlostowski@cern.ch>
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
...
...
@@ -31,8 +32,6 @@ use work.wishbone_pkg.all;
library
unisim
;
use
unisim
.
vcomponents
.
all
;
entity
spec_top
is
generic
(
g_riscv_firmware
:
string
:
=
"uart-bootloader.ram"
;
...
...
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