core: fixed unwanted destination register write when a MUL instruction is…

core: fixed unwanted destination register write when a MUL instruction is followed by a stalling instruction

core: fixed unwanted destination register write when a MUL instruction is…
core: fixed unwanted destination register write when a MUL instruction is followed by a stalling instruction
4db75631 · Tomasz Wlostowski · d7bc65d4 · 4db75631 · 4db75631 · 4db75631
Commit 4db75631 authored Nov 13, 2018 by Tomasz Wlostowski
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Showing with 22 additions and 19 deletions

urv_exec.v rtl/urv_exec.v +19 -16

urv_multiply.v rtl/urv_multiply.v +2 -2

urv_regfile.v rtl/urv_regfile.v +1 -1

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--- a/rtl/urv_exec.v
+++ b/rtl/urv_exec.v
@@ -508,23 +508,26 @@ module urv_exec
 	w_store_o <= 0;
 	w_valid_o <= 0;
 	
-     end else if (!x_stall_i) begin
-	  f_branch_target_o <= branch_target;
-	  f_branch_take <= branch_take && !x_kill_i && d_valid_i;
-          f_dbg_toggle_o <= g_with_hw_debug && d_is_ebreak_i && !x_kill_i && d_valid_i;
-          w_rd_o <= d_rd_i;
-	  w_rd_value_o <= rd_value;
-
-	  w_rd_write_o <= d_rd_write_i && !x_kill_i && d_valid_i && !x_exception;
-	  w_load_o <= d_is_load_i && !x_kill_i && d_valid_i && !x_exception;
-	  w_store_o <= d_is_store_i && !x_kill_i && d_valid_i && !x_exception;
-
-	  w_rd_source_o <= d_rd_source_i;
-	  w_fun_o <= d_fun_i;
-	  w_dm_addr_o <= dm_addr;
-	  w_valid_o <= !x_exception;
-     end // else: !if(rst_i)
+     end else begin
+	w_valid_o <= !x_exception && !x_stall_i;

+	if (!x_stall_i) begin
+	   f_branch_target_o <= branch_target;
+           w_rd_o <= d_rd_i;
+	   w_rd_value_o <= rd_value;
+	   
+	   f_branch_take <= branch_take && !x_kill_i && d_valid_i;
+           f_dbg_toggle_o <= g_with_hw_debug && d_is_ebreak_i && !x_kill_i && d_valid_i;
+  	   w_rd_write_o <= d_rd_write_i && !x_kill_i && d_valid_i && !x_exception;
+	   w_load_o <= d_is_load_i && !x_kill_i && d_valid_i && !x_exception;
+	   w_store_o <= d_is_store_i && !x_kill_i && d_valid_i && !x_exception;
+
+	   w_rd_source_o <= d_rd_source_i;
+	   w_fun_o <= d_fun_i;
+	   w_dm_addr_o <= dm_addr;
+	end
+     end // else: !if(rst_i)
+   
   always@*
     exception_pc <= d_pc_i;
   

--- a/rtl/urv_multiply.v
+++ b/rtl/urv_multiply.v
@@ -201,8 +201,8 @@ module urv_multiply
   reg 	     mul_stall_req;
   reg 		     mul_stall_req_d0;
   reg 		     mul_stall_req_d1;
-   
-   
+
+
   urv_mult18x18 mul0
     (
      .clk_i(clk_i),

--- a/rtl/urv_regfile.v
+++ b/rtl/urv_regfile.v
@@ -92,7 +92,7 @@ module urv_regfile

   wire [31:0] rs1_regfile;
   wire [31:0] rs2_regfile;
-   wire        write  = (!d_stall_i && w_rd_store_i && (w_rd_i != 0));
+   wire        write  = (w_rd_store_i && (w_rd_i != 0));

   urv_regmem bank0
     (