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Created with Raphaël 2.2.025Sep3Dec9Nov8765432131Oct3029282726252423222119Sep98530Aug2827262523212019181715141312532119Julworking on the plan B, WIPtom-sep25tom-sep25Only terminate 1st channel + increase test clock frequencymastermasterdoc: first version of the test reportdoc: demonstration designdemo: update dependsdoc: new datadoc: cleanup datadoc: cleanup LUT and HIS datadoc: add differential measurement histogramsdoc: replace gnuplot with matplotlibdoc: specify larger recovery time (needed by preinversion)doc: added raw measurement resultsPre-inversiondoc: explain extra histogram bitsdoc: structuredemo: feedback through one IOB (optional)Support for extra histogram bitsdoc: include picturesdoc: temperature dependence of rodoc: FPGA Editor screenshotsdemo: floorplan ring oscillatorsdemo: floorplan calibration signal muxes and delay linesdemo: reset TDC core at startuprotest: enable terminations, lower frequencydemo: I2C workingdemo: DAC I2C access (untested)demo: enable terminations on FMC DIOdemo: slower test clockdemo: unsigned printfdemo: CSV rofreqdemo: fix multichannel calinfodemo: display temperature with ring osc frequencydemo: differential measurementsRevert "demo: add HPLL and serial_dac design files from White Rabbit r1344"demo: add inttypes.hdemo: add HPLL and serial_dac design files from White Rabbit r1344Documentation updatedemo: temperature sensor workingdemo: 1wire GPIO access + resetdelayline: reorder taps by increasing delays