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Commit b9a492c5 authored by Sebastien Bourdeauducq's avatar Sebastien Bourdeauducq
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Pre-inversion

parent bc11ddc1
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core/tdc_channel.vhd
+ 9
− 3
View file @ b9a492c5
......@@ -12,6 +12,7 @@
--
-------------------------------------------------------------------------------
-- last changes:
-- 2011-11-07 SB Pre-inversion
-- 2011-10-25 SB Disable ring oscillator on reset
-- 2011-08-03 SB Created file
-------------------------------------------------------------------------------
......@@ -90,7 +91,9 @@ end entity;
architecture rtl of tdc_channel is
signal calib_sel_d : std_logic;
signal muxed_signal : std_logic;
signal inv_signal : std_logic;
signal taps : std_logic_vector(4*g_CARRY4_COUNT-1 downto 0);
signal ipolarity : std_logic;
signal polarity : std_logic;
signal polarity_d1 : std_logic;
signal polarity_d2 : std_logic;
......@@ -110,6 +113,7 @@ begin
end process;
with calib_sel_d select
muxed_signal <= calib_i when '1', signal_i when others;
inv_signal <= muxed_signal xor not ipolarity;
cmp_delayline: tdc_delayline
generic map(
......@@ -118,19 +122,21 @@ begin
port map(
clk_i => clk_i,
reset_i => reset_i,
signal_i => muxed_signal,
signal_i => inv_signal,
taps_o => taps
);
cmp_lbc: tdc_lbc
generic map(
g_N => g_RAW_COUNT,
g_NIN => g_CARRY4_COUNT*4
g_N => g_RAW_COUNT,
g_NIN => g_CARRY4_COUNT*4,
g_IGNORE => 2
)
port map(
clk_i => clk_i,
reset_i => reset_i,
d_i => taps,
ipolarity_o => ipolarity,
polarity_o => polarity,
count_o => raw
);
......
core/tdc_lbc.vhd
+ 40
− 5
View file @ b9a492c5
......@@ -12,6 +12,7 @@
--
-------------------------------------------------------------------------------
-- last changes:
-- 2011-11-07 SB Pre-inversion
-- 2011-10-27 SB Fix pipeline balance
-- 2011-08-01 SB Created file
-------------------------------------------------------------------------------
......@@ -41,14 +42,17 @@ use work.tdc_package.all;
entity tdc_lbc is
generic(
-- Number of output bits.
g_N : positive;
g_N : positive;
-- Number of input bits. Maximum is 2^g_N-1.
g_NIN: positive
g_NIN : positive;
-- Number of cycles to ignore input after a transition.
g_IGNORE : natural
);
port(
clk_i : in std_logic;
reset_i : in std_logic;
d_i : in std_logic_vector(g_NIN-1 downto 0);
ipolarity_o : out std_logic;
polarity_o : out std_logic;
count_o : out std_logic_vector(g_N-1 downto 0)
);
......@@ -97,6 +101,7 @@ signal polarity_d1 : std_logic;
signal count : std_logic_vector(g_N-1 downto 0);
signal count_d1 : std_logic_vector(g_N-1 downto 0);
signal d_completed : std_logic_vector(2**g_N-2 downto 0);
signal ignore : std_logic;
-- enable retiming
attribute register_balancing: string;
......@@ -105,7 +110,7 @@ attribute register_balancing of count_d1: signal is "backward";
begin
g_expand: if g_NIN < 2**g_N-1 generate
d_completed <= d_i & (2**g_N-1-g_NIN-1 downto 0 => not polarity);
d_completed <= d_i & (2**g_N-1-g_NIN-1 downto 0 => '0');
end generate;
g_dontexpand: if g_NIN = 2**g_N-1 generate
d_completed <= d_i;
......@@ -120,13 +125,43 @@ begin
count <= (others => '0');
count_d1 <= (others => '0');
else
polarity <= not d_completed(2**g_N-2);
if (d_completed(2**g_N-2) = '1') and (ignore = '0') then
polarity <= not polarity;
end if;
polarity_d1 <= not polarity;
count <= f_cls(d_completed, polarity);
count <= f_cls(d_completed, '1');
count_d1 <= count;
end if;
end if;
end process;
g_ignoresr: if g_IGNORE > 0 generate
signal ignore_sr: std_logic_vector(g_IGNORE-1 downto 0);
begin
process(clk_i)
begin
if rising_edge(clk_i) then
if reset_i = '1' then
ignore_sr <= (others => '0');
else
if (d_completed(2**g_N-2) = '1') and (ignore = '0') then
ignore_sr <= (others => '0');
ignore_sr(g_IGNORE-1) <= '1';
else
ignore_sr <= "0" & ignore_sr(g_IGNORE-1 downto 1);
end if;
end if;
end if;
end process;
ignore <= '0' when (ignore_sr = (ignore_sr'range => '0')) else '1';
end generate;
g_noignore: if g_IGNORE = 0 generate
begin
ignore <= '0';
end generate;
ipolarity_o <= polarity;
polarity_o <= polarity_d1;
count_o <= count_d1;
end architecture;
core/tdc_package.vhd
+ 5
− 2
View file @ b9a492c5
......@@ -12,6 +12,7 @@
--
-------------------------------------------------------------------------------
-- last changes:
-- 2011-11-07 SB Pre-inversion
-- 2011-11-05 SB Added extra histogram bits support
-- 2011-10-25 SB Added single/multi channel bank components
-- 2011-08-03 SB Created file
......@@ -339,13 +340,15 @@ end component;
component tdc_lbc is
generic(
g_N : positive;
g_NIN : positive
g_N : positive;
g_NIN : positive;
g_IGNORE : natural
);
port(
clk_i : in std_logic;
reset_i : in std_logic;
d_i : in std_logic_vector(g_NIN-1 downto 0);
ipolarity_o : out std_logic;
polarity_o : out std_logic;
count_o : out std_logic_vector(g_N-1 downto 0)
);
......
demo/boards/spec/synthesis/common.ucf
+ 4
− 4
View file @ b9a492c5
......@@ -41,11 +41,11 @@ NET "tdc_signal_p[1]" LOC = W12 | IOSTANDARD = "LVDS_25";
NET "tdc_signal_n[1]" LOC = Y12 | IOSTANDARD = "LVDS_25";
# ==== TDC core ====
NET "tdc/cmp_tdc/cmp_channelbank/g_multi.cmp_channelbank/g_channels[0].cmp_channel/muxed_signal" TIG;
NET "tdc/cmp_tdc/cmp_channelbank/g_multi.cmp_channelbank/g_channels[1].cmp_channel/muxed_signal" TIG;
NET "tdc/cmp_tdc/cmp_channelbank/g_multi.cmp_channelbank/g_channels[0].cmp_channel/inv_signal" TIG;
NET "tdc/cmp_tdc/cmp_channelbank/g_multi.cmp_channelbank/g_channels[1].cmp_channel/inv_signal" TIG;
INST "tdc/cmp_tdc/cmp_channelbank/g_multi.cmp_channelbank/g_channels[0].cmp_channel/Mmux_muxed_signal11" LOC = SLICE_X35Y0;
INST "tdc/cmp_tdc/cmp_channelbank/g_multi.cmp_channelbank/g_channels[1].cmp_channel/Mmux_muxed_signal11" LOC = SLICE_X35Y0;
INST "tdc/cmp_tdc/cmp_channelbank/g_multi.cmp_channelbank/g_channels[0].cmp_channel/Mxor_inv_signal_xo<0>1" LOC = SLICE_X35Y0;
INST "tdc/cmp_tdc/cmp_channelbank/g_multi.cmp_channelbank/g_channels[1].cmp_channel/Mxor_inv_signal_xo<0>1" LOC = SLICE_X35Y0;
INST "tdc/cmp_tdc/cmp_channelbank/g_multi.cmp_channelbank/g_channels[0].cmp_channel/cmp_delayline/g_carry4[0].g_firstcarry4.cmp_CARRY4" LOC = SLICE_X30Y2;
INST "tdc/cmp_tdc/cmp_channelbank/g_multi.cmp_channelbank/g_channels[1].cmp_channel/cmp_delayline/g_carry4[0].g_firstcarry4.cmp_CARRY4" LOC = SLICE_X32Y2;
tb/lbc/tb_lbc.vhd
+ 20
− 13
View file @ b9a492c5
......@@ -12,6 +12,7 @@
--
-------------------------------------------------------------------------------
-- last changes:
-- 2011-11-07 SB Pre-inversion
-- 2011-08-12 SB Test pipelining and polarity inversion
-- 2011-08-03 SB Created file
-------------------------------------------------------------------------------
......@@ -93,24 +94,27 @@ begin
return result;
end function;
signal clk : std_logic;
signal reset : std_logic;
signal d : std_logic_vector(2**g_N-2 downto 0);
signal count : std_logic_vector(g_N-1 downto 0);
signal polarity : std_logic;
signal clk : std_logic;
signal reset : std_logic;
signal d : std_logic_vector(2**g_N-2 downto 0);
signal count : std_logic_vector(g_N-1 downto 0);
signal ipolarity : std_logic;
signal polarity : std_logic;
begin
cmp_dut: tdc_lbc
generic map(
g_N => g_N,
g_NIN => 2**g_N-1
g_N => g_N,
g_NIN => 2**g_N-1,
g_IGNORE => 0
)
port map(
clk_i => clk,
reset_i => reset,
d_i => d,
count_o => count,
polarity_o => polarity
clk_i => clk,
reset_i => reset,
d_i => d,
ipolarity_o => ipolarity,
polarity_o => polarity,
count_o => count
);
process
variable v_polarity : std_logic;
......@@ -122,6 +126,7 @@ begin
variable v_stim : std_logic_vector(0 downto 0);
begin
-- reset
d <= (others => '0');
reset <= '1';
clk <= '0';
wait for 5 ns;
......@@ -150,7 +155,9 @@ begin
end if;
end loop;
report "Vector out: " & str(v_d) & " (polarity: " & chr(v_polarity) & ")";
d <= v_d;
for j in 0 to 2**g_N-2 loop
d(j) <= v_d(j) xor not ipolarity;
end loop;
end if;
-- verify output
if i > 2 then
......
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