Per-channel processing: add LUT

core/tdc_channel.vhd

@@ -19,22 +19,38 @@
 
 library ieee;
 use ieee.std_logic_1164.all;
+
+library work;
 use work.tdc_package.all;
+use work.genram_pkg.all;
 
 entity tdc_channel is
     generic(
         -- Number of CARRY4 elements.
         g_CARRY4_COUNT : positive;
         -- Number of raw output bits.
-        g_RAW_COUNT    : positive
+        g_RAW_COUNT    : positive;
+        -- Number of fractional part bits.
+        g_FP_COUNT     : positive
     );
     port(
          clk_i        : in std_logic;
          reset_i      : in std_logic;
+         
+         -- Signal input.
          signal_i     : in std_logic;
+         
+         -- Detection outputs.
          detect_o     : out std_logic;
          polarity_o   : out std_logic;
-         raw_o        : out std_logic_vector(g_RAW_COUNT-1 downto 0)
+         raw_o        : out std_logic_vector(g_RAW_COUNT-1 downto 0);
+         fp_o         : out std_logic_vector(g_FP_COUNT-1 downto 0);
+         
+         -- LUT access.
+         lut_a_i      : in std_logic_vector(g_RAW_COUNT-1 downto 0);
+         lut_we_i     : in std_logic;
+         lut_d_i      : in std_logic_vector(g_FP_COUNT-1 downto 0);
+         lut_d_o      : out std_logic_vector(g_FP_COUNT-1 downto 0)
     );
 end entity;
 
@@ -54,6 +70,8 @@ begin
              taps_o       => taps
         );
     
+    -- TODO: reorder bits by increasing delays
+    
     cmp_lbc: tdc_lbc
         generic map(
             g_N     => g_RAW_COUNT,
@@ -67,6 +85,32 @@ begin
              count_o      => raw
         );
     
+    cmp_lut: generic_dpram
+        generic map(
+            g_data_width               => g_FP_COUNT,
+            g_size                     => 2**g_RAW_COUNT,
+            g_with_byte_enable         => false,
+            g_addr_conflict_resolution => "read_first",
+            g_init_file                => "",
+            g_dual_clock               => false
+        )
+        port map(
+            clka_i => clk_i,
+            clkb_i => '0',
+            
+            wea_i  => '0',
+            bwea_i => (others => '0'),
+            aa_i   => raw,
+            da_i   => (others => '0'),
+            qa_o   => fp_o,
+            
+            web_i  => lut_we_i,
+            bweb_i => (others => '0'),
+            ab_i   => lut_a_i,
+            db_i   => lut_d_i,
+            qb_o   => lut_d_o
+        );
+    
     polarity_o <= polarity_d1;
     
     process(clk_i)

core/tdc_delayline.vhd

@@ -20,8 +20,11 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-library UNISIM;
-use UNISIM.vcomponents.all;
+library unisim;
+use unisim.vcomponents.all;
+
+library work;
+use work.tdc_package.all;
 
 entity tdc_delayline is
     generic(

core/tdc_lbc.vhd

@@ -20,8 +20,11 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
+library work;
+use work.tdc_package.all;
+
 entity tdc_lbc is
-    generic (
+    generic(
         -- Number of output bits.
         g_N : positive;
         -- Number of input bits. Maximum is 2^g_N-1.

core/tdc_package.vhd

@@ -23,7 +23,7 @@ use ieee.std_logic_1164.all;
 package tdc_package is
 
 component tdc_lbc is
-    generic (
+    generic(
         g_N : positive;
         g_NIN: positive
     );

tb/lbc/tb_lbc.vhd

@@ -23,6 +23,8 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use ieee.math_real.all;
+
+library work;
 use work.tdc_package.all;
 
 entity tb_lbc is
@@ -37,17 +39,17 @@ function chr(sl: std_logic) return character is
 variable v_c: character;
 begin
     case sl is
-        when 'U' => v_c:= 'U';
-        when 'X' => v_c:= 'X';
-        when '0' => v_c:= '0';
-        when '1' => v_c:= '1';
-        when 'Z' => v_c:= 'Z';
-        when 'W' => v_c:= 'W';
-        when 'L' => v_c:= 'L';
-        when 'H' => v_c:= 'H';
-        when '-' => v_c:= '-';
+        when 'U' => v_c := 'U';
+        when 'X' => v_c := 'X';
+        when '0' => v_c := '0';
+        when '1' => v_c := '1';
+        when 'Z' => v_c := 'Z';
+        when 'W' => v_c := 'W';
+        when 'L' => v_c := 'L';
+        when 'H' => v_c := 'H';
+        when '-' => v_c := '-';
     end case;
-return v_c;
+    return v_c;
 end function;
 
 function str(slv: std_logic_vector) return string is
@@ -84,11 +86,11 @@ begin
         );
     reset <= '0';
     process
-    variable v_seed1     : positive := 1;
-    variable v_seed2     : positive := 2;
-    variable v_rand      : real;
-    variable v_int_rand  : integer;
-    variable v_stim      : std_logic_vector(0 downto 0); 
+    variable v_seed1    : positive := 1;
+    variable v_seed2    : positive := 2;
+    variable v_rand     : real;
+    variable v_int_rand : integer;
+    variable v_stim     : std_logic_vector(0 downto 0); 
     begin
         -- reset
         reset <= '1';