Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
P
pcie-vme-bridge
Manage
Activity
Members
Code
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Deploy
Releases
Analyze
Contributor analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
This is an archived project. Repository and other project resources are read-only.
hdl-core-lib
pcie-vme-bridge
Commits
f1cdc993
Commit
f1cdc993
authored
8 years ago
by
Michael Miehling
Committed by
GitHub
8 years ago
Browse files
Options
Downloads
Patches
Plain Diff
Update README.md
parent
fda7e09e
No related merge requests found
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
README.md
+7
-5
7 additions, 5 deletions
README.md
with
7 additions
and
5 deletions
README.md
+
7
−
5
View file @
f1cdc993
...
...
@@ -59,13 +59,15 @@ Synthesis: Altera Quartus synthesis files
How to generate a new programming file:
1)
Edit chameleon_V2.xls in order to set new revision (Page "Content", minor revision in C8, major revision in C7) and close xl
s
1)
Copy Synthesis/quartus.ini file in Quartus installation folder /quartus/bin64/ in order to support EPCS32 serial flash device
s
2)
call
cham
2.bat for hex file generation
2)
Edit
cham
eleon_V2.xls in order to set new revision (Page "Content", minor revision in C8, major revision in C7) and close xls
3)
Edit Synthesis/gen_programming_files.tcl and change programming file name to new revision in variable PROJECT_RELEASE_NAM "16A025-00_MM_mm"
3)
call cham2.bat for hex file generation
4)
open A25_top.qpf in Quartus 15.1
4)
Edit Synthesis/gen_programming_files.tcl and change programming file name to new revision in variable PROJECT_RELEASE_NAM "16A025-00_MM_mm"
5) Run synthesis: if successful, new files with name 16A025-00_MM_mm will be generated in Synthesis/fpga_files
5) open A25_top.qpf in Quartus 15.1
6) Run synthesis: if successful, new files with name 16A025-00_MM_mm will be generated in Synthesis/fpga_files
This diff is collapsed.
Click to expand it.
Preview
0%
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment