not using Arria DPRAM for PCI to WB FIFO

454bcec9 · Dusan Slavinec · 175285ac · 454bcec9 · 454bcec9
Commit 454bcec9 authored Oct 06, 2015 by Dusan Slavinec
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Showing with 2 additions and 4 deletions

Manifest.py Manifest.py +1 -3

pci_user_constants.v src/hdl/verilog/pci_user_constants.v +1 -1

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--- a/Manifest.py
+++ b/Manifest.py
@@ -60,8 +60,6 @@ files = [
  "src/hdl/verilog/timescale.v",
  "src/hdl/wb_pci_pkg.vhd",
  "src/hdl/wb_pmc_host_bridge.vhd",
-  "src/hdl/wb_pmc_host_bridge_pkg.vhd",
-  "src/hdl/dpram/aria_dpram.v",
-  "src/hdl/dpram/aria_dpram.qip",
+  "src/hdl/wb_pmc_host_bridge_pkg.vhd"
 ];

--- a/src/hdl/verilog/pci_user_constants.v
+++ b/src/hdl/verilog/pci_user_constants.v
@@ -126,7 +126,7 @@
        `define WB_FIFO_RAM_ADDR_LENGTH 8       // WB slave unit fifo storage definition
 //        `define WB_CYCLONEII_DPRAM		// Select CYCLONEII Dual Port Memory	
 //        `define PCI_CYCLONEII_DPRAM		// Select CYCLONEII Dual Port Memory	
-          `define ALTERA_ARRIA_V_DPRAM
+//          `define ALTERA_ARRIA_V_DPRAM
    `endif
 `else
    `define PCI_FIFO_RAM_ADDR_LENGTH 8      // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )