adding pci core files

175285ac · Dusan Slavinec · f84af5e8 · 175285ac · 175285ac · 175285ac
Commit 175285ac authored Oct 06, 2015 by Dusan Slavinec
70 changed files
--- a/Manifest.py
+++ b/Manifest.py
@@ -60,6 +60,8 @@ files = [
  "src/hdl/verilog/timescale.v",
  "src/hdl/wb_pci_pkg.vhd",
  "src/hdl/wb_pmc_host_bridge.vhd",
-  "src/hdl/wb_pmc_host_bridge_pkg.vhd"
+  "src/hdl/wb_pmc_host_bridge_pkg.vhd",
+  "src/hdl/dpram/aria_dpram.v",
+  "src/hdl/dpram/aria_dpram.qip",
 ];

--- a/src/hdl/dpram/aria_dpram.cmp
+++ b/src/hdl/dpram/aria_dpram.cmp
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component aria_dpram
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		clock_a		: IN STD_LOGIC  := '1';
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (39 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (39 DOWNTO 0);
+		rden_a		: IN STD_LOGIC  := '1';
+		rden_b		: IN STD_LOGIC  := '1';
+		wren_a		: IN STD_LOGIC  := '0';
+		wren_b		: IN STD_LOGIC  := '0';
+		q_a		: OUT STD_LOGIC_VECTOR (39 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (39 DOWNTO 0)
+	);
+end component;
--- a/src/hdl/dpram/aria_dpram.inc
+++ b/src/hdl/dpram/aria_dpram.inc
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION aria_dpram 
+(
+	address_a[7..0],
+	address_b[7..0],
+	clock_a,
+	clock_b,
+	data_a[39..0],
+	data_b[39..0],
+	rden_a,
+	rden_b,
+	wren_a,
+	wren_b
+)
+
+RETURNS (
+	q_a[39..0],
+	q_b[39..0]
+);
--- a/src/hdl/dpram/aria_dpram.qip
+++ b/src/hdl/dpram/aria_dpram.qip
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "aria_dpram.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "aria_dpram_inst.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "aria_dpram_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "aria_dpram.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "aria_dpram.cmp"]
--- a/src/hdl/dpram/aria_dpram.v
+++ b/src/hdl/dpram/aria_dpram.v
--- a/src/hdl/dpram/aria_dpram_bb.v
+++ b/src/hdl/dpram/aria_dpram_bb.v
+// megafunction wizard: %RAM: 2-PORT%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: aria_dpram.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.4 Build 182 03/12/2014 SJ Full Version
+// ************************************************************
+
+//Copyright (C) 1991-2014 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+module aria_dpram (
+	address_a,
+	address_b,
+	clock_a,
+	clock_b,
+	data_a,
+	data_b,
+	rden_a,
+	rden_b,
+	wren_a,
+	wren_b,
+	q_a,
+	q_b);
+
+	input	[7:0]  address_a;
+	input	[7:0]  address_b;
+	input	  clock_a;
+	input	  clock_b;
+	input	[39:0]  data_a;
+	input	[39:0]  data_b;
+	input	  rden_a;
+	input	  rden_b;
+	input	  wren_a;
+	input	  wren_b;
+	output	[39:0]  q_a;
+	output	[39:0]  q_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock_a;
+	tri1	  rden_a;
+	tri1	  rden_b;
+	tri0	  wren_a;
+	tri0	  wren_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "5"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria V"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "10240"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "40"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "40"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "40"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "40"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria V"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "40"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "40"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
+// Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL "address_a[7..0]"
+// Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL "address_b[7..0]"
+// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
+// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
+// Retrieval info: USED_PORT: data_a 0 0 40 0 INPUT NODEFVAL "data_a[39..0]"
+// Retrieval info: USED_PORT: data_b 0 0 40 0 INPUT NODEFVAL "data_b[39..0]"
+// Retrieval info: USED_PORT: q_a 0 0 40 0 OUTPUT NODEFVAL "q_a[39..0]"
+// Retrieval info: USED_PORT: q_b 0 0 40 0 OUTPUT NODEFVAL "q_b[39..0]"
+// Retrieval info: USED_PORT: rden_a 0 0 0 0 INPUT VCC "rden_a"
+// Retrieval info: USED_PORT: rden_b 0 0 0 0 INPUT VCC "rden_b"
+// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+// Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
+// Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
+// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 40 0 data_a 0 0 40 0
+// Retrieval info: CONNECT: @data_b 0 0 40 0 data_b 0 0 40 0
+// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden_a 0 0 0 0
+// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden_b 0 0 0 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+// Retrieval info: CONNECT: q_a 0 0 40 0 @q_a 0 0 40 0
+// Retrieval info: CONNECT: q_b 0 0 40 0 @q_b 0 0 40 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL aria_dpram.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL aria_dpram.inc TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL aria_dpram.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL aria_dpram.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL aria_dpram_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL aria_dpram_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
--- a/src/hdl/dpram/aria_dpram_inst.v
+++ b/src/hdl/dpram/aria_dpram_inst.v
+aria_dpram	aria_dpram_inst (
+	.address_a ( address_a_sig ),
+	.address_b ( address_b_sig ),
+	.clock_a ( clock_a_sig ),
+	.clock_b ( clock_b_sig ),
+	.data_a ( data_a_sig ),
+	.data_b ( data_b_sig ),
+	.rden_a ( rden_a_sig ),
+	.rden_b ( rden_b_sig ),
+	.wren_a ( wren_a_sig ),
+	.wren_b ( wren_b_sig ),
+	.q_a ( q_a_sig ),
+	.q_b ( q_b_sig )
+	);
--- a/src/hdl/dpram/greybox_tmp/cbx_args.txt
+++ b/src/hdl/dpram/greybox_tmp/cbx_args.txt
+ADDRESS_REG_B=CLOCK1
+CLOCK_ENABLE_INPUT_A=BYPASS
+CLOCK_ENABLE_INPUT_B=BYPASS
+CLOCK_ENABLE_OUTPUT_A=BYPASS
+CLOCK_ENABLE_OUTPUT_B=BYPASS
+INDATA_REG_B=CLOCK1
+INTENDED_DEVICE_FAMILY="Arria V"
+LPM_TYPE=altsyncram
+NUMWORDS_A=256
+NUMWORDS_B=256
+OPERATION_MODE=BIDIR_DUAL_PORT
+OUTDATA_ACLR_A=NONE
+OUTDATA_ACLR_B=NONE
+OUTDATA_REG_A=CLOCK0
+OUTDATA_REG_B=CLOCK1
+POWER_UP_UNINITIALIZED=FALSE
+READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ
+READ_DURING_WRITE_MODE_PORT_B=NEW_DATA_NO_NBE_READ
+WIDTHAD_A=8
+WIDTHAD_B=8
+WIDTH_A=40
+WIDTH_B=40
+WIDTH_BYTEENA_A=1
+WIDTH_BYTEENA_B=1
+WRCONTROL_WRADDRESS_REG_B=CLOCK1
+DEVICE_FAMILY="Arria V"
+address_a
+address_b
+clock0
+clock1
+data_a
+data_b
+rden_a
+rden_b
+wren_a
+wren_b
+q_a
+q_b
--- a/src/hdl/verilog/bus_commands.v
+++ b/src/hdl/verilog/bus_commands.v
--- a/src/hdl/verilog/pci_async_reset_flop.v
+++ b/src/hdl/verilog/pci_async_reset_flop.v
--- a/src/hdl/verilog/pci_bridge32.v
+++ b/src/hdl/verilog/pci_bridge32.v
@@ -221,8 +221,14 @@ module pci_bridge32
    // system error pin
    pci_serr_o,
    pci_serr_oe_o,
-    pci_bar_hit_o
-
+    
+    // MSI capability registers
+`ifdef MSI_CAPABILITY_EN
+    msi_control_o,
+    msi_address_o,
+    msi_msg_data_o,    
+`endif
+    
 `ifdef PCI_BIST
    ,
    // debug chain signals
@@ -373,7 +379,21 @@ output  pci_perr_oe_o ;
 output  pci_serr_o ;
 output  pci_serr_oe_o ;

-output [5:0] pci_bar_hit_o ;
+output  [31 : 0]	msi_control_o;
+output  [31 : 0]	msi_address_o;
+output  [15 : 0]	msi_msg_data_o;
+
+`ifdef MSI_CAPABILITY_EN
+  assign msi_control_o    = conf_msi_control;
+  assign msi_address_o    = conf_msi_address;
+  assign msi_msg_data_o   = conf_msi_msg_data;
+`else
+  assign msi_control_o    = 32'h0000_0000;
+  assign msi_address_o    = 32'h0000_0000;
+  assign msi_msg_data_o   = 16'h0000;
+`endif
+
+

 `ifdef PCI_BIST
 /*-----------------------------------------------------
@@ -596,6 +616,13 @@ wire            conf_int_out ;
 wire            conf_wb_init_complete_out  ;
 wire            conf_pci_init_complete_out ;

+// MSI capability registers to top
+wire  [31 : 0]	conf_msi_control;
+wire  [31 : 0]	conf_msi_address;
+wire  [15 : 0]	conf_msi_msg_data;
+
+
+
 // PCI IO MUX OUTPUTS
 wire        pci_mux_frame_out ;
 wire        pci_mux_irdy_out ;
@@ -1186,8 +1213,7 @@ pci_target_unit pci_target_unit
    .pciu_conf_be_out               (pciu_conf_be_out),
    .pciu_conf_data_out             (pciu_conf_data_out),
    .pciu_pci_drcomp_pending_out    (pciu_pci_drcomp_pending_out),
-    .pciu_pciw_fifo_empty_out       (pciu_pciw_fifo_empty_out),
-    .pciu_bar_hit_o                 (pci_bar_hit_o)
+    .pciu_pciw_fifo_empty_out       (pciu_pciw_fifo_empty_out)

 `ifdef PCI_BIST
    ,
@@ -1366,6 +1392,14 @@ pci_conf_space configuration(

                                .pci_init_complete_out      (conf_pci_init_complete_out),
                                .wb_init_complete_out       (conf_wb_init_complete_out)
+                                
+                                `ifdef MSI_CAPABILITY_EN
+                                    ,
+                                    .msi_control         (conf_msi_control),
+                                    .msi_address         (conf_msi_address),
+                                    .msi_msg_data        (conf_msi_msg_data)
+                                `endif
+                                

                            `ifdef PCI_CPCI_HS_IMPLEMENT
                                ,

--- a/src/hdl/verilog/pci_cbe_en_crit.v
+++ b/src/hdl/verilog/pci_cbe_en_crit.v
--- a/src/hdl/verilog/pci_conf_cyc_addr_dec.v
+++ b/src/hdl/verilog/pci_conf_cyc_addr_dec.v
--- a/src/hdl/verilog/pci_conf_space.v
+++ b/src/hdl/verilog/pci_conf_space.v
--- a/src/hdl/verilog/pci_constants.v
+++ b/src/hdl/verilog/pci_constants.v
@@ -90,8 +90,14 @@
 // This does not include address offsets of PCI Header registers - they starts at offset 0 (see PCI spec.)
 //   ALL VALUES are without 2 LSBits AND there is required that address bit [8] is set while
 //   accessing this registers, otherwise the configuration header will be accessed !!!
-`define PCI_CAP_PTR_VAL         8'h80
-`define P_IMG_CTRL0_ADDR		6'h00	//	Address offset = h 100
+
+`define P_MSI_CAP_PTR_VAL     8'h50  
+`define P_MSI_MSG_CTRL        6'h14  // Address offset for MSI capability = h 50
+`define P_MSI_MSG_ADDR        6'h15  // Address offset for MSI capability = h 54
+`define P_MSI_MSG_DATA        6'h16  // Address offset for MSI capability = h 58
+
+`define PCI_CAP_PTR_VAL   8'h80
+`define P_IMG_CTRL0_ADDR	6'h00	//	Address offset = h 100
 `define P_BA0_ADDR				6'h01	//	Address offset = h 104
 `define P_AM0_ADDR				6'h02   //	Address offset = h 108
 `define P_TA0_ADDR				6'h03   //	Address offset = h 10c
@@ -159,6 +165,8 @@
 `endif
 `endif

+
+
 // all flip-flops in the design have this inter-assignment delay
 `define FF_DELAY 1

--- a/src/hdl/verilog/pci_cur_out_reg.v
+++ b/src/hdl/verilog/pci_cur_out_reg.v
--- a/src/hdl/verilog/pci_delayed_sync.v
+++ b/src/hdl/verilog/pci_delayed_sync.v
--- a/src/hdl/verilog/pci_delayed_write_reg.v
+++ b/src/hdl/verilog/pci_delayed_write_reg.v
--- a/src/hdl/verilog/pci_frame_crit.v
+++ b/src/hdl/verilog/pci_frame_crit.v
--- a/src/hdl/verilog/pci_frame_en_crit.v
+++ b/src/hdl/verilog/pci_frame_en_crit.v
--- a/src/hdl/verilog/pci_frame_load_crit.v
+++ b/src/hdl/verilog/pci_frame_load_crit.v
--- a/src/hdl/verilog/pci_in_reg.v
+++ b/src/hdl/verilog/pci_in_reg.v
--- a/src/hdl/verilog/pci_io_mux.v
+++ b/src/hdl/verilog/pci_io_mux.v
--- a/src/hdl/verilog/pci_io_mux_ad_en_crit.v
+++ b/src/hdl/verilog/pci_io_mux_ad_en_crit.v
--- a/src/hdl/verilog/pci_io_mux_ad_load_crit.v
+++ b/src/hdl/verilog/pci_io_mux_ad_load_crit.v
--- a/src/hdl/verilog/pci_irdy_out_crit.v
+++ b/src/hdl/verilog/pci_irdy_out_crit.v
--- a/src/hdl/verilog/pci_mas_ad_en_crit.v
+++ b/src/hdl/verilog/pci_mas_ad_en_crit.v
--- a/src/hdl/verilog/pci_mas_ad_load_crit.v
+++ b/src/hdl/verilog/pci_mas_ad_load_crit.v
--- a/src/hdl/verilog/pci_mas_ch_state_crit.v
+++ b/src/hdl/verilog/pci_mas_ch_state_crit.v
--- a/src/hdl/verilog/pci_master32_sm.v
+++ b/src/hdl/verilog/pci_master32_sm.v
--- a/src/hdl/verilog/pci_master32_sm_if.v
+++ b/src/hdl/verilog/pci_master32_sm_if.v
--- a/src/hdl/verilog/pci_out_reg.v
+++ b/src/hdl/verilog/pci_out_reg.v
--- a/src/hdl/verilog/pci_par_crit.v
+++ b/src/hdl/verilog/pci_par_crit.v
--- a/src/hdl/verilog/pci_parity_check.v
+++ b/src/hdl/verilog/pci_parity_check.v
--- a/src/hdl/verilog/pci_pci_decoder.v
+++ b/src/hdl/verilog/pci_pci_decoder.v
--- a/src/hdl/verilog/pci_pci_tpram.v
+++ b/src/hdl/verilog/pci_pci_tpram.v
@@ -397,6 +397,34 @@ input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift cont
    assign do_a = 0 ;
 `endif

+`ifdef ALTERA_ARRIA_V_DPRAM
+    `define PCI_PCI_RAM_SELECTED
+    //
+    // Instantiation of FPGA RAM:
+    //
+    // Altera ARRIA V Synchronous 2-port R/W RAM
+    //
+	aria_dpram	aria_dpram_inst (
+		.address_a ( addr_a ),
+		.address_b ( addr_b ), 
+		.clock_a   ( clk_a ),
+		.clock_b   ( clk_b ),
+		.data_a    ( di_a ),
+		.data_b    ( di_a ),
+		.rden_a    ( oe_a ),
+		.rden_b    ( oe_b ),
+		.wren_a    ( we_a ),
+		.wren_b    ( we_a ),
+		.q_a       ( do_a ),
+		.q_b       ( do_b )
+		);
+	 
+`endif
+
+
+
+
+
 `ifdef PCI_PCI_RAM_SELECTED
 `else
    //

--- a/src/hdl/verilog/pci_pcir_fifo_control.v
+++ b/src/hdl/verilog/pci_pcir_fifo_control.v
--- a/src/hdl/verilog/pci_pciw_fifo_control.v
+++ b/src/hdl/verilog/pci_pciw_fifo_control.v
--- a/src/hdl/verilog/pci_pciw_pcir_fifos.v
+++ b/src/hdl/verilog/pci_pciw_pcir_fifos.v
--- a/src/hdl/verilog/pci_perr_crit.v
+++ b/src/hdl/verilog/pci_perr_crit.v
--- a/src/hdl/verilog/pci_perr_en_crit.v
+++ b/src/hdl/verilog/pci_perr_en_crit.v
--- a/src/hdl/verilog/pci_ram_16x40d.v
+++ b/src/hdl/verilog/pci_ram_16x40d.v
--- a/src/hdl/verilog/pci_rst_int.v
+++ b/src/hdl/verilog/pci_rst_int.v
--- a/src/hdl/verilog/pci_serr_crit.v
+++ b/src/hdl/verilog/pci_serr_crit.v
--- a/src/hdl/verilog/pci_serr_en_crit.v
+++ b/src/hdl/verilog/pci_serr_en_crit.v
--- a/src/hdl/verilog/pci_spoci_ctrl.v
+++ b/src/hdl/verilog/pci_spoci_ctrl.v
--- a/src/hdl/verilog/pci_sync_module.v
+++ b/src/hdl/verilog/pci_sync_module.v
--- a/src/hdl/verilog/pci_synchronizer_flop.v
+++ b/src/hdl/verilog/pci_synchronizer_flop.v
--- a/src/hdl/verilog/pci_target32_clk_en.v
+++ b/src/hdl/verilog/pci_target32_clk_en.v
--- a/src/hdl/verilog/pci_target32_devs_crit.v
+++ b/src/hdl/verilog/pci_target32_devs_crit.v
--- a/src/hdl/verilog/pci_target32_interface.v
+++ b/src/hdl/verilog/pci_target32_interface.v
@@ -48,9 +48,6 @@
 // Specification updated.
 // Test application changed to support WB B3 cycles.
 //
-// Revision 2.0 2015/02/09 dusan slavinec
-// Added bar_hit_out output.
-//
 // Revision 1.9  2003/08/21 20:55:14  tadejm
 // Corrected bug when writing to FIFO (now it is registered).
 //
@@ -208,8 +205,7 @@ module pci_target32_interface
 	addr_tran_en2_in,
 	addr_tran_en3_in,
 	addr_tran_en4_in,
-	addr_tran_en5_in,
-  bar_hit_out //
+	addr_tran_en5_in
 ) ;

 `ifdef HOST
@@ -388,8 +384,6 @@ input			addr_tran_en3_in ;	// address translation enable bit
 input			addr_tran_en4_in ;	// address translation enable bit
 input			addr_tran_en5_in ;	// address translation enable bit

-output [5:0]  bar_hit_out ; // bar hit vector
-
 /*==================================================================================================================
 END of input / output PORT DEFINITONS !!!
 ==================================================================================================================*/
@@ -468,8 +462,6 @@ wire			pre_fetch_en5 = 1'b0 ;



-assign bar_hit_out = {hit5_in, hit4_in, hit3_in, hit2_in, hit1_in, hit0_in};
-
 // Include address decoders
 `ifdef			HOST
 	`ifdef		NO_CNF_IMAGE

--- a/src/hdl/verilog/pci_target32_sm.v
+++ b/src/hdl/verilog/pci_target32_sm.v
--- a/src/hdl/verilog/pci_target32_stop_crit.v
+++ b/src/hdl/verilog/pci_target32_stop_crit.v
--- a/src/hdl/verilog/pci_target32_trdy_crit.v
+++ b/src/hdl/verilog/pci_target32_trdy_crit.v
--- a/src/hdl/verilog/pci_target_unit.v
+++ b/src/hdl/verilog/pci_target_unit.v
@@ -40,8 +40,6 @@
 //////////////////////////////////////////////////////////////////////
 //
 // CVS Revision History
-// Revision 1.15  2015/02/09 dslavinec
-// Added pciu_bar_hit_o output (PCI bar hit)
 //
 // $Log: not supported by cvs2svn $
 // Revision 1.15  2003/12/19 11:11:30  mihad
@@ -108,9 +106,6 @@ module pci_target_unit
    reset_in,
    wb_clock_in,
    pci_clock_in,
-    
-    pciu_bar_hit_o, // dslavinec
-
    pciu_wbm_adr_o,
    pciu_wbm_dat_o,
    pciu_wbm_dat_i,
@@ -312,8 +307,6 @@ output  [31:0]  pciu_conf_data_out ;
 output          pciu_pci_drcomp_pending_out ;
 output          pciu_pciw_fifo_empty_out ;

-output [5:0]    pciu_bar_hit_o; // dslavinec
-
 `ifdef PCI_BIST
 /*-----------------------------------------------------
 BIST debug chain port signals
@@ -844,8 +837,7 @@ pci_target32_interface pci_target_if
    .addr_tran_en2_in               (pcit_if_addr_tran_en2_in),
    .addr_tran_en3_in               (pcit_if_addr_tran_en3_in),
    .addr_tran_en4_in               (pcit_if_addr_tran_en4_in),
-    .addr_tran_en5_in               (pcit_if_addr_tran_en5_in),
-    .bar_hit_out                    (pciu_bar_hit_o)
+    .addr_tran_en5_in               (pcit_if_addr_tran_en5_in)
 ) ;

 // pci target state machine inputs

--- a/src/hdl/verilog/pci_user_constants.v
+++ b/src/hdl/verilog/pci_user_constants.v
@@ -106,7 +106,8 @@

 `define FPGA
 //`define XILINX
-`define ALTERA
+`define ALTERA
+

 `define WB_RAM_DONT_SHARE
 `define PCI_RAM_DONT_SHARE
@@ -123,8 +124,9 @@
    `ifdef ALTERA
        `define PCI_FIFO_RAM_ADDR_LENGTH 8      // PCI target unit fifo storage definition
        `define WB_FIFO_RAM_ADDR_LENGTH 8       // WB slave unit fifo storage definition
-        `define WB_CYCLONEII_DPRAM		// Select CYCLONEII Dual Port Memory	
-        `define PCI_CYCLONEII_DPRAM		// Select CYCLONEII Dual Port Memory	
+//        `define WB_CYCLONEII_DPRAM		// Select CYCLONEII Dual Port Memory	
+//        `define PCI_CYCLONEII_DPRAM		// Select CYCLONEII Dual Port Memory	
+          `define ALTERA_ARRIA_V_DPRAM
    `endif
 `else
    `define PCI_FIFO_RAM_ADDR_LENGTH 8      // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
@@ -156,7 +158,7 @@
 // allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images,
 // you have to define a number of minimum sized image and enlarge others by specifying different address mask.
 // smaller the number here, faster the decoder operation
-`define PCI_NUM_OF_DEC_ADDR_LINES 8
+`define PCI_NUM_OF_DEC_ADDR_LINES 20

 // no. of PCI Target IMAGES
 // - PCI provides 6 base address registers for image implementation.
@@ -185,12 +187,12 @@
 // won't detect base address implemented and device dependent software will have to configure
 // address masks as well as base addresses!
 // Don't define PCI_AMx to 24'hffff_ff for memory images! Use that just for I/O images.
-`define PCI_AM0 24'hff00_f0
-`define PCI_AM1 24'h7fff_f0
+`define PCI_AM0 24'hffff_f0
+`define PCI_AM1 24'hffff_f0
 `define PCI_AM2 24'hff00_00
-`define PCI_AM3 24'h7fff_f0
-`define PCI_AM4 24'hff00_00
-`define PCI_AM5 24'h7fff_f0
+`define PCI_AM3 24'hffff_f0
+`define PCI_AM4 24'hffff_f0
+`define PCI_AM5 24'hffff_f0

 // initial value for PCI image maping to MEMORY or IO spaces.  If initial define is set to 0,
 // then IMAGE with that base address points to MEMORY space, othervise it points ti IO space. D
@@ -205,16 +207,16 @@
 // initial value for PCI translation addresses. The  initial values
 // are set after reset. When ADDR_TRAN_IMPL is defined then then Images 
 // are transleted to this adresses whithout access to pci_ta registers.
-`define PCI_TA0 24'h0000_0
-`define PCI_TA1 24'h0100_0
-`define PCI_TA2 24'h0200_0
-`define PCI_TA3 24'h0000_0
-`define PCI_TA4 24'h0000_0
-`define PCI_TA5 24'h0000_0
+`define PCI_TA0 24'h0000_00
+`define PCI_TA1 24'h0100_00
+`define PCI_TA2 24'h0200_00
+`define PCI_TA3 24'h0000_00
+`define PCI_TA4 24'h0000_00
+`define PCI_TA5 24'h0000_00

 `define PCI_AT_EN0 1'b0
-`define PCI_AT_EN1 1'b0
-`define PCI_AT_EN2 1'b0
+`define PCI_AT_EN1 1'b1
+`define PCI_AT_EN2 1'b1
 `define PCI_AT_EN3 1'b0
 `define PCI_AT_EN4 1'b0
 `define PCI_AT_EN5 1'b0
@@ -231,15 +233,15 @@
 // ( both GUEST and NO_CNF_IMAGE defined ), then WB image 0 is not implemented. User doesn't need to define image 0.
 // WB Image 1 is always implemented and user doesnt need to specify its definition
 // WB images' 2 through 5 implementation by defining each one.
-`define WB_IMAGE2
+//`define WB_IMAGE2
 //`define WB_IMAGE3
 //`define WB_IMAGE4
 //`define WB_IMAGE5

 //Address bar register defines the base address for each image.
 //To asccess bus without Software configuration.
-`define  WB_BA1	20'h0100_0
-`define  WB_BA2	20'h0200_0
+`define  WB_BA1	20'hfee0_1
+`define  WB_BA2	20'h3810_0
 `define  WB_BA3	20'h3820_0
 `define  WB_BA4	20'h3830_0
 `define  WB_BA5	20'h3840_0
@@ -253,9 +255,9 @@
 `define  WB_BA5_MEM_IO	1'b0  

 // initial value for WB image address masks. 
-`define  WB_AM1 20'hff00_0
-`define  WB_AM2 20'hff00_0
-`define  WB_AM3 20'h7fff_0
+`define  WB_AM1 20'hffff_f
+`define  WB_AM2 20'h7f00_0
+`define  WB_AM3 20'h7ff0_0
 `define  WB_AM4 20'h7ff0_0
 `define  WB_AM5 20'h7ff0_0

@@ -268,18 +270,18 @@
 `define WB_AT_EN4 1'b0
 `define WB_AT_EN5 1'b0

-`define WB_TA1 20'h0100_0
-`define WB_TA2 20'h0200_0
-`define WB_TA3 20'h0300_0
-`define WB_TA4 20'h0400_0
-`define WB_TA5 20'h0500_0
+`define WB_TA1 20'h0400_0
+`define WB_TA2 20'h0800_0
+`define WB_TA3 20'h0000_0
+`define WB_TA4 20'h0000_0
+`define WB_TA5 20'h0000_0


 // If this define is commented out, then address translation will not be implemented.
 // addresses will pass through bridge unchanged, regardles of address translation enable bits.
 // Address translation also slows down the decoding
 //When  ADDR_TRAN_IMPL this define is present then adress translation is enabled after reset.
-//`define ADDR_TRAN_IMPL
+`define ADDR_TRAN_IMPL

 // decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.
 // slower decode speed can be used, to provide enough time for address to be decoded.
@@ -316,8 +318,8 @@ capable device
 //`define HEADER_MAX_LAT          8'h1a
 //`define HEADER_MIN_GNT          8'h08

-`define HEADER_VENDOR_ID        16'h10dc
-`define HEADER_DEVICE_ID        16'hbeef
+`define HEADER_VENDOR_ID        16'h10dc // CERN
+`define HEADER_DEVICE_ID        16'hc570
 `define HEADER_REVISION_ID      8'h01
 `define HEADER_SUBSYS_VENDOR_ID 16'h10dc
 `define HEADER_SUBSYS_ID        16'hbeef
@@ -336,6 +338,9 @@ capable device
 `define PCI_WB_REV_B3
 //`define PCI_WBS_B3_RTY_DISABLE

+// enables MSI capabitlity for triggering interrupts
+`define MSI_CAPABILITY_EN
+
 `ifdef GUEST
 //    `define PCI_CPCI_HS_IMPLEMENT
 //    `define PCI_SPOCI

--- a/src/hdl/verilog/pci_wb_addr_mux.v
+++ b/src/hdl/verilog/pci_wb_addr_mux.v
--- a/src/hdl/verilog/pci_wb_decoder.v
+++ b/src/hdl/verilog/pci_wb_decoder.v
--- a/src/hdl/verilog/pci_wb_master.v
+++ b/src/hdl/verilog/pci_wb_master.v
--- a/src/hdl/verilog/pci_wb_slave.v
+++ b/src/hdl/verilog/pci_wb_slave.v
--- a/src/hdl/verilog/pci_wb_slave_unit.v
+++ b/src/hdl/verilog/pci_wb_slave_unit.v
--- a/src/hdl/verilog/pci_wb_tpram.v
+++ b/src/hdl/verilog/pci_wb_tpram.v
--- a/src/hdl/verilog/pci_wbr_fifo_control.v
+++ b/src/hdl/verilog/pci_wbr_fifo_control.v
--- a/src/hdl/verilog/pci_wbs_wbb3_2_wbb2.v
+++ b/src/hdl/verilog/pci_wbs_wbb3_2_wbb2.v
--- a/src/hdl/verilog/pci_wbw_fifo_control.v
+++ b/src/hdl/verilog/pci_wbw_fifo_control.v
--- a/src/hdl/verilog/pci_wbw_wbr_fifos.v
+++ b/src/hdl/verilog/pci_wbw_wbr_fifos.v
--- a/src/hdl/verilog/timescale.v
+++ b/src/hdl/verilog/timescale.v
--- a/src/hdl/wb_pci_pkg.vhd
+++ b/src/hdl/wb_pci_pkg.vhd
@@ -168,8 +168,9 @@ port (
    wbm_rty_i            : in      std_logic;
    wbm_err_i            : in      std_logic;

-
-    pci_bar_hit_o        : out     std_logic_vector(5 downto 0);
+   	msi_control_o        : out     std_logic_vector(31 downto 0);
+    msi_address_o        : out     std_logic_vector(31 downto 0);
+    msi_msg_data_o       : out     std_logic_vector(15 downto 0);
    
 -- pci interface - system pins
    pci_clk_i            : in      std_logic;

--- a/src/hdl/wb_pmc_host_bridge.vhd
+++ b/src/hdl/wb_pmc_host_bridge.vhd
@@ -11,6 +11,7 @@ use work.wishbone_pkg.all;
 use work.genram_pkg.all;
 use work.wb_pci_pkg.all;
 --use work.wb_pmc_host_bridge_pkg.all;
+use work.gencores_pkg.all;

 -- XWB control BAR is mapped to BAR1
 -- XWB devices BAR is mapped to BAR2
@@ -34,15 +35,18 @@ entity wb_pmc_host_bridge is
    slave_rstn_i  : in    std_logic := '1';
    slave_i       : in    t_wishbone_slave_in;
    slave_o       : out   t_wishbone_slave_out;
+    
    -- PCI signals - generic
    pci_clk_i     : in    std_logic := '0';
    pci_rst_i     : in    std_logic := '0';
    buf_oe_o      : out   std_logic := '0';
    busmode_io    : inout std_logic_vector(3 downto 0);
+    
    -- PCI signals (required) - address and data
    ad_io         : inout std_logic_vector(31 downto 0);
    c_be_io       : inout std_logic_vector(3 downto 0);
    par_io        : inout std_logic;
+    
    -- PCI signals (required) - interface control pins
    frame_io      : inout std_logic;
    trdy_io       : inout std_logic;
@@ -50,9 +54,13 @@ entity wb_pmc_host_bridge is
    stop_io       : inout std_logic;
    devsel_io     : inout std_logic;
    idsel_i       : in    std_logic;
+    req_o         : out   std_logic;
+    gnt_i         : in    std_logic;
+    
    -- PCI signals (required) - error reporting
    perr_io       : inout std_logic;
    serr_io       : inout std_logic;
+    
    -- PCI signals (optional) - interrupts pins
    inta_o        : out   std_logic
 );    
@@ -92,6 +100,11 @@ signal wbs_rty      : std_logic;
 signal wbs_err      : std_logic;
 signal wbs_cti      : std_logic_vector(2 downto 0);
 signal wbs_bte      : std_logic_vector(1 downto 0);
+signal wbs_stall    : std_logic;
+
+signal msi_control  : std_logic_vector(31 downto 0);
+signal msi_address  : std_logic_vector(31 downto 0);
+signal msi_msg_data : std_logic_vector(15 downto 0);

 -- Wishbone Master Interface
 signal wbm_adr      : std_logic_vector(31 downto 0);
@@ -138,7 +151,6 @@ signal SERR_en      : std_logic;
  signal internal_wb_clk, internal_wb_rstn, stall : std_logic; 
  signal internal_wb_rstn_sync : std_logic_vector(3 downto 0) := (others => '0');
  
-  signal tx_alloc_mask : std_logic := '1'; -- Only pass every even tx32_alloc to tx64_alloc.
  
  signal wb_stb   : std_logic;
  signal wb_cyc   : std_logic;
@@ -174,8 +186,9 @@ signal SERR_en      : std_logic;
  signal stb_asserted : std_logic;
  signal ack_asserted : std_logic; 

-  signal pci_bar_hit      : std_logic_vector(5 downto 0);
-  signal r_pci_bar_hit    : std_logic_vector(5 downto 0);
+  signal irq_key_state    : std_logic;
+  signal irq_key_down     : std_logic;
+  signal irq_key_up       : std_logic;
  

 begin
@@ -198,10 +211,10 @@ port map (
 pci_inta_oe_o  => INTA_en,

 -- arbitration pins
- pci_req_o      => REQ_out, -- not used in GUEST
- pci_req_oe_o   => REQ_en,  -- not used in GUEST
+ pci_req_o      => REQ_out,
+ pci_req_oe_o   => REQ_en,

- pci_gnt_i      => '1',     -- not used in GUEST
+ pci_gnt_i      => gnt_i,

 -- protocol pins
 pci_frame_i      => frame_io,
@@ -248,27 +261,29 @@ port map (
 pci_serr_o       => SERR_out,
 pci_serr_oe_o    => SERR_en, 

- pci_bar_hit_o    => pci_bar_hit,
+ msi_control_o   => open,
+ msi_address_o   => msi_address,
+ msi_msg_data_o  => msi_msg_data,

 -- WISHBONE system signals
 wb_clk_i   => wb_clk,
 wb_rst_i   => wb_rst_in,
 wb_rst_o   => wb_rst_out,
 
- wb_int_i   => '0', -- wb_int_in,
+ wb_int_i   => wb_int_in,
 wb_int_o   => open,  -- not used in GUEST

 -- WISHBONE slave interface
- wbs_adr_i  => (others => '0'),
- wbs_dat_i  => (others => '0'),
- wbs_dat_o  => open,
- wbs_sel_i  => (others => '0'),
- wbs_cyc_i  => '0',
- wbs_stb_i  => '0',
- wbs_we_i   => '0',
- wbs_ack_o  => open,
- wbs_rty_o  => open,
- wbs_err_o  => open,
+ wbs_adr_i  => wbs_adr,
+ wbs_dat_i  => wbs_dat_in,
+ wbs_dat_o  => wbs_dat_out,
+ wbs_sel_i  => wbs_sel,
+ wbs_cyc_i  => wbs_cyc,
+ wbs_stb_i  => wbs_stb,
+ wbs_we_i   => wbs_we,
+ wbs_ack_o  => wbs_ack_out,
+ wbs_rty_o  => wbs_rty,
+ wbs_err_o  => wbs_err,
 
 --`ifdef PCI_WB_REV_B3
 wbs_cti_i  => (others => '0'),
@@ -317,11 +332,11 @@ devsel_io <=  DEVSEL_out  when DEVSEL_en  = BUF_OE else 'Z';
 trdy_io   <=  TRDY_out    when TRDY_en    = BUF_OE else 'Z';
 stop_io   <=  STOP_out    when STOP_en    = BUF_OE else 'Z';
 inta_o    <=  INTA_out    when INTA_en    = BUF_OE else 'Z';
+req_o     <=  REQ_out     when REQ_en     = BUF_OE else 'Z';
 par_io    <=  PAR_out     when PAR_en     = BUF_OE else 'Z';
 perr_io   <=  PERR_out    when PERR_en    = BUF_OE else 'Z';
 serr_io   <=  SERR_out    when SERR_en    = BUF_OE else 'Z';

--req_o     <= 'Z'; -- not used in GUEST


 busmode_io(3 downto 1)  <= (others => 'Z'); -- only used as inputs
@@ -373,29 +388,18 @@ end process p_bus_activitiy_fsm;

 -- rising edge detectors
 stb_asserted <= '1' when (stb_prev = '0' and wbm_stb = '1') else '0';
-ack_asserted <= '1' when (ack_prev = '0' and  wb_ack = '1') else '0';
+ack_asserted <= '1' when (ack_prev = '0' and wb_ack  = '1') else '0';

 wb_stb  <= wbm_stb when bus_state = st_idle else '0';


--------------------------------------------------------------------
-- bar hit register - store bar hit vector from PCI core when it changes
-p_bar_hit_reg: process(internal_wb_clk)
-begin
-  if rising_edge(internal_wb_clk) then
-    if internal_wb_rstn = '0' then
-      r_pci_bar_hit <= (others => '0');
-    else 
-      if pci_bar_hit /= "000000" and pci_bar_hit /= r_pci_bar_hit then
-        r_pci_bar_hit <= pci_bar_hit;
-      else 
-        r_pci_bar_hit <= r_pci_bar_hit;
-      end if;
-    end if; -- reset
-  end if; -- clk
-end process p_bar_hit_reg;
-
-wb_bar  <= r_pci_bar_hit;
+-- Using ADDRESS TRANSLATION feature of the PCI core to get bar_hit
+-- see ./verilog/pci_user_constants.v : 
+-- `define PCI_TA1 24'h0100_00
+-- `define PCI_TA2 24'h0200_00
+-- BAR1 on WB address bus is translated from 0xPPxxxxxx on PCI > 0x01xxxxxx on WB
+-- BAR2 on WB address bus is translated from 0xPPxxxxxx on PCI > 0x02xxxxxx on WB
+wb_bar  <= wbm_adr(28 downto 24) & '0';

 wb_adr          <= x"00000000" & wbm_adr;

@@ -419,7 +423,6 @@ wbm_dat_in  <= wb_dat;
  begin
    if rising_edge(internal_wb_clk) then
      internal_wb_rstn_sync <= (master_rstn_i and slave_rstn_i) & internal_wb_rstn_sync(internal_wb_rstn_sync'length-1 downto 1);
-      
    end if;
  end process;
  
@@ -454,8 +457,41 @@ wbm_dat_in  <= wb_dat;
  fifo_full <= int_master_o.cyc and int_master_o.stb;
  app_int_sts <= fifo_full and r_int; -- Classic interrupt until FIFO drained
  app_msi_req <= fifo_full and not r_fifo_full; -- Edge-triggered MSI
+
+wb_int_in <= app_int_sts; -- connect generated IRQ signal to PCI core signal
  
  int_master_i.rty <= '0';
+wbs_stall <= '0' when wbs_cyc = '0' else not wbs_ack_out;
+-- send pending MSI IRQs over WB
+  wb_irq_master : process(internal_wb_clk)
+  begin
+   if rising_edge(internal_wb_clk) then
+      if(internal_wb_rstn = '0') then
+         wbs_cyc <= '0';
+         wbs_stb <= '0';
+      else
+         if wbs_cyc = '1' then
+           if wbs_stall = '0' then
+             wbs_stb <= '0';
+           end if;
+           if (wbs_ack_out = '1' or wbs_err = '1') then
+             wbs_cyc <= '0';
+           end if;
+         else
+           wbs_cyc <= app_msi_req;
+           wbs_stb <= app_msi_req;
+           wbs_adr    <= msi_address; 
+           wbs_dat_in <= x"0000" & msi_msg_data;
+         end if;
+      end if;
+    end if;
+  end process;  
+  
+-- Wishbone Slave Interface !!! Used for posting MSI
+wbs_sel      <= "1111"; 
+wbs_we       <= '1';
+wbs_rty      <= '0';
+wbs_bte      <= "00";  
  
  control : process(internal_wb_clk)
  begin

--- a/src/hdl/wb_pmc_host_bridge_pkg.vhd
+++ b/src/hdl/wb_pmc_host_bridge_pkg.vhd
@@ -18,35 +18,40 @@ package wb_pmc_host_bridge_pkg is
      g_family   : string := "Arria V";
      g_sdb_addr : t_wishbone_address);
    port (
-      -- FPGA signals
-      clk_sys_i     : in  std_logic;
-      rst_n_i       : in  std_logic;
-      -- Commands from PMC to FPGA
-      master_clk_i  : in    std_logic := '0';
-      master_rstn_i : in    std_logic := '1';
-      master_o      : out   t_wishbone_master_out;
-      master_i      : in    t_wishbone_master_in;
-      -- Command to PMC from FPGA
-      slave_clk_i   : in    std_logic := '0';
-      slave_rstn_i  : in    std_logic := '1';
-      slave_i       : in    t_wishbone_slave_in;
-      slave_o       : out   t_wishbone_slave_out;
-      -- PCI signals - generic
-      pci_clk_i     : in    std_logic := '0';
-      pci_rst_i     : in    std_logic := '0';
-      buf_oe_o      : out   std_logic;
-      busmode_io    : inout std_logic_vector(3 downto 0);
-      -- PCI signals (required) - address and data
-      ad_io         : inout std_logic_vector(31 downto 0);
-      c_be_io       : inout std_logic_vector(3 downto 0);
-      par_io        : inout std_logic;
-      -- PCI signals (required) - interface control pins
-      frame_io      : inout std_logic;
-      trdy_io       : inout std_logic;
-      irdy_io       : inout std_logic;
-      stop_io       : inout std_logic;
-      devsel_io     : inout std_logic;
-      idsel_i       : in    std_logic;
+    -- FPGA signals
+    clk_sys_i     : in  std_logic;
+    rst_n_i       : in  std_logic;
+    -- Commands from PMC to FPGA
+    master_clk_i  : in    std_logic := '0';
+    master_rstn_i : in    std_logic := '1';
+    master_o      : out   t_wishbone_master_out;
+    master_i      : in    t_wishbone_master_in;
+    -- Command to PMC from FPGA
+    slave_clk_i   : in    std_logic := '0';
+    slave_rstn_i  : in    std_logic := '1';
+    slave_i       : in    t_wishbone_slave_in;
+    slave_o       : out   t_wishbone_slave_out;
+    
+    -- PCI signals - generic
+    pci_clk_i     : in    std_logic := '0';
+    pci_rst_i     : in    std_logic := '0';
+    buf_oe_o      : out   std_logic := '0';
+    busmode_io    : inout std_logic_vector(3 downto 0);
+    
+    -- PCI signals (required) - address and data
+    ad_io         : inout std_logic_vector(31 downto 0);
+    c_be_io       : inout std_logic_vector(3 downto 0);
+    par_io        : inout std_logic;
+    
+    -- PCI signals (required) - interface control pins
+    frame_io      : inout std_logic;
+    trdy_io       : inout std_logic;
+    irdy_io       : inout std_logic;
+    stop_io       : inout std_logic;
+    devsel_io     : inout std_logic;
+    idsel_i       : in    std_logic;
+    req_o         : out   std_logic;
+    gnt_i         : in    std_logic;
      -- PCI signals (required) - error reporting
      perr_io       : inout std_logic;
      serr_io       : inout std_logic;