hdl: minor style and indentation fixes.

a3c94bad · Tristan Gingold · 5118dc11 · a3c94bad · a3c94bad · a3c94bad
Commit a3c94bad authored Jul 25, 2018 by Tristan Gingold
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Showing with 50 additions and 58 deletions

mt_rmq_rx.vhd hdl/rtl/mqueue/mt_rmq_rx.vhd +8 -10

mt_rmq_tx.vhd hdl/rtl/mqueue/mt_rmq_tx.vhd +41 -47

main.sv hdl/testbench/mock_turtle_core/main.sv +1 -1

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--- a/hdl/rtl/mqueue/mt_rmq_rx.vhd
+++ b/hdl/rtl/mqueue/mt_rmq_rx.vhd
@@ -107,30 +107,30 @@ begin
                       wmask => "XXXX");
            n_state <= state;
          end if;
-        when CLAIM =>

+        when CLAIM =>
          n_state <= state;

          snk_o <= (pkt_ready => '1',
                    ready     => '1');

-
-
          if snk_i.valid = '1' then
            --  Data available, store it.
            outb_o <= (sel   => '1',
                       adr   => std_logic_vector(state.addr),
-                       dat   => snk_i.data(7 downto 0) & snk_i.data(15 downto 8) &                                 snk_i.data(7 downto 0) & snk_i.data(15 downto 8),
+                       dat   => (snk_i.data(7 downto 0)
+                                 & snk_i.data(15 downto 8)
+                                 & snk_i.data(7 downto 0)
+                                 & snk_i.data(15 downto 8)),
                       we    => '1',
                       wmask => "0000");

-            if(state.is_even = '1') then
+            if state.is_even = '1' then
              outb_o.wmask <= "0011";
            else
              outb_o.wmask <= "1100";
            end if;

-            
            if snk_i.error = '1' then
              -- Error (in the packet) or packet dropped by the EP filter
              n_state.state <= WAIT_SLOT;
@@ -149,7 +149,6 @@ begin
                n_state.payload_size <= to_unsigned(2, 13);
                n_state.is_hdr_d     <= '0';
              else
-
                n_state.state <= CLAIM;
                n_state.is_hdr_d <= snk_i.hdr;
                n_state.is_even <= not state.is_even;
@@ -157,7 +156,7 @@ begin
                if(snk_i.hdr = '0') then
                  n_state.payload_size <= state.payload_size + 2;
                end if;
-                
+
                if state.is_even = '1' then
                  n_state.addr <= state.addr;
                else
@@ -175,7 +174,6 @@ begin
            n_state <= state;
          end if;

-
        when WRITE_SIZE =>
          --  Make the slot ready.
          snk_o <= (pkt_ready => '0',
@@ -198,7 +196,7 @@ begin
          outb_o <= (sel            => '1',
                     adr            => c_mqueue_addr_command,
                     dat            => (c_mqueue_command_ready => '1',
-                             others => '0'),
+                                        others => '0'),
                     we             => '1',
                     wmask          => "1111");
          n_state <= (state   => WAIT_SLOT,

--- a/hdl/rtl/mqueue/mt_rmq_tx.vhd
+++ b/hdl/rtl/mqueue/mt_rmq_tx.vhd
@@ -76,37 +76,34 @@ begin
                dat   => (others => 'X'),
                we    => 'X',
                wmask => "XXXX");
-      src_o <= (
-        req   => not inb_stat_i.empty,
-        data  => (others => 'X'),
-        hdr   => 'X',
-        valid => '0',
-        last  => 'X',
-        error => 'X');
+      src_o <= (req   => not inb_stat_i.empty,
+                data  => (others => 'X'),
+                hdr   => 'X',
+                valid => '0',
+                last  => 'X',
+                error => 'X');
      n_state <= (state         => WAIT_SLOT,
                  addr          => (others => 'X'),
                  pkt_last_addr => (others => 'X'));
    else
      n_state <= state;
-      src_o <= (
-        req   => not inb_stat_i.empty,
-        data  => (others => 'X'),
-        hdr   => 'X',
-        valid => '0',
-        last  => 'X',
-        error => '0');
+      src_o <= (req   => not inb_stat_i.empty,
+                data  => (others => 'X'),
+                hdr   => 'X',
+                valid => '0',
+                last  => 'X',
+                error => '0');

      case state.state is
        when WAIT_SLOT =>
          if inb_stat_i.empty = '0' then
            --  A packet can be read and sent.  Claim it.
-            inb_o <= (
-              sel            => '1',
-              adr            => c_mqueue_addr_command,
-              dat            => (c_mqueue_command_claim => '1',
-                      others => '0'),
-              we             => '1',
-              wmask          => "1111");
+            inb_o <= (sel            => '1',
+                      adr            => c_mqueue_addr_command,
+                      dat            => (c_mqueue_command_claim => '1',
+                                         others => '0'),
+                      we             => '1',
+                      wmask          => "1111");

            n_state <= (state         => CLAIM,
                        addr          => unsigned(c_mqueue_addr_header_size),
@@ -132,20 +129,19 @@ begin
        when SEND_HEADER =>
          --if state.addr = unsigned(c_mqueue_addr_header(12 downto 2)) then
          --  Save packet length.
-          if(src_i.ready = '1') then
-            n_state.pkt_last_addr <= unsigned("1" & inb_i.dat(10 downto 0) & "00" ) - 4;
+          if src_i.ready = '1' then
+            n_state.pkt_last_addr <=
+              unsigned("1" & inb_i.dat(10 downto 0) & "00" ) - 4;
          end if;

-          src_o <= (
-
-            req   => not inb_stat_i.empty,
-            data  => inb_i.dat,
-            hdr   => '1',
-            valid => '1',
-            last  => '0',
-            error => '0');
+          src_o <= (req   => not inb_stat_i.empty,
+                    data  => inb_i.dat,
+                    hdr   => '1',
+                    valid => '1',
+                    last  => '0',
+                    error => '0');

-          if(src_i.ready = '1')then
+          if src_i.ready = '1' then
            n_state.state <= SEND_PAYLOAD_EVEN;
            n_state.addr  <= unsigned(c_mqueue_addr_payload);

@@ -178,13 +174,12 @@ begin
                    wmask => "XXXX");

          --  Send payload word
-          src_o <= (
-            req   => not inb_stat_i.empty,
-            data  => x"0000" & inb_i.dat(31 downto 16) ,
-            hdr   => '0',
-            valid => '1',
-            last  => '0',
-            error => '0');
+          src_o <= (req   => not inb_stat_i.empty,
+                    data  => x"0000" & inb_i.dat(31 downto 16),
+                    hdr   => '0',
+                    valid => '1',
+                    last  => '0',
+                    error => '0');

          if src_i.ready = '1' then
              n_state <= (state         => SEND_PAYLOAD_ODD,
@@ -202,13 +197,12 @@ begin
                    wmask => "XXXX");

          --  Send payload word
-          src_o <= (
-            req   => not inb_stat_i.empty,
-            data  => x"0000" & inb_i.dat(15 downto 0) ,
-            hdr   => '0',
-            valid => '1',
-            last  => payload_last,
-            error => '0');
+          src_o <= (req   => not inb_stat_i.empty,
+                    data  => x"0000" & inb_i.dat(15 downto 0) ,
+                    hdr   => '0',
+                    valid => '1',
+                    last  => payload_last,
+                    error => '0');

          if src_i.ready = '1' then
            if payload_last = '1' then
@@ -229,7 +223,7 @@ begin
            end if;
          end if;

-          
+
        when DISCARD =>
          --  Need to wait one cycle so that empty status  is updated.
          n_state <= (state         => WAIT_SLOT,

--- a/hdl/testbench/mock_turtle_core/main.sv
+++ b/hdl/testbench/mock_turtle_core/main.sv
@@ -71,7 +71,7 @@ module main;

   assign ep2mt.snk_in[0][0] = mt2ep.src_out[0][0];
   assign ep2mt.src_in[0][0] = mt2ep.snk_out[0][0];
-   
+
   IVHDWishboneMaster Host ( clk_sys, rst_n );

   IMockTurtleIRQ IrqMonitor (`MT_ATTACH_IRQ(DUT));