hdl: add tx_error signal from gn4142 to l2p dma state machine.

tx_error acts as the abort signal.

hdl/gn4124core/rtl/l2p_dma_master.vhd

@@ -81,6 +81,7 @@ entity l2p_dma_master is
       l2p_edb_o  : out std_logic;                     -- Asserted when transfer is aborted
       l_wr_rdy_i : in  std_logic_vector(1 downto 0);  -- Asserted when GN4124 is ready to receive master write
       l2p_rdy_i  : in  std_logic;                     -- De-asserted to pause transfer already in progress
+      tx_error_i : in  std_logic;                     -- Asserted when unexpected or malformed packet recevied
 
       ---------------------------------------------------------
       -- DMA Interface (Pipelined Wishbone)
@@ -407,7 +408,7 @@ begin
             ldm_arb_valid_o <= '0';
           end if;
 
-          if (dma_ctrl_abort_i = '1') then
+          if (dma_ctrl_abort_i = '1' or tx_error_i = '1') then
             l2p_edb_o             <= '1';
             l2p_dma_current_state <= L2P_IDLE;
           elsif (l2p_rdy_i = '0') then

hdl/gn4124core/rtl/spartan6/gn4124_core.vhd

@@ -247,6 +247,9 @@ architecture rtl of gn4124_core is
   signal l2p_edb       : std_logic;
   signal l2p_edb_t     : std_logic;
   signal l2p_edb_t2    : std_logic;
+  signal tx_error_t2   : std_logic;
+  signal tx_error_t    : std_logic;
+  signal tx_error      : std_logic;
 
   -------------------------------------------------------------
   -- CSR wishbone master to arbiter
@@ -630,6 +633,7 @@ begin
       l2p_edb_o  => l2p_edb,
       l_wr_rdy_i => l_wr_rdy,
       l2p_rdy_i  => l2p_rdy,
+      tx_error_i => tx_error,
 
       l2p_dma_clk_i   => dma_clk_i,
       l2p_dma_adr_o   => l2p_dma_adr,
@@ -764,6 +768,9 @@ begin
       l2p_edb_o     <= '0';
       l2p_edb_t     <= '0';
       l2p_edb_t2    <= '0';
+      tx_error_t2   <= '0';
+      tx_error_t    <= '0';
+      tx_error      <= '0';
     elsif rising_edge(sys_clk) then
       -- must be checked before l2p_dma_master issues a master write
       l_wr_rdy_t  <= l_wr_rdy_i;
@@ -780,6 +787,11 @@ begin
       l2p_rdy_t2 <= l2p_rdy_t;
       l2p_rdy    <= l2p_rdy_t2;
 
+      -- when asserted, stop dma transfer. Should never be asserted under normal operation conditions!
+      tx_error_t  <= tx_error_i;
+      tx_error_t2 <= tx_error_t;
+      tx_error    <= tx_error_t2;
+
       --assert when packet badly ends (e.g. dma abort)
       l2p_edb_t  <= l2p_edb;
       l2p_edb_t2 <= l2p_edb_t;

hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd

@@ -397,6 +397,7 @@ package gn4124_core_pkg is
         l2p_edb_o  : out std_logic;                     -- Asserted when transfer is aborted
         l_wr_rdy_i : in  std_logic_vector(1 downto 0);  -- Asserted when GN4124 is ready to receive master write
         l2p_rdy_i  : in  std_logic;                     -- De-asserted to pause transfer already in progress
+        tx_error_i : in  std_logic;                     -- Transmit Error
 
         ---------------------------------------------------------
         -- DMA Interface (Pipelined Wishbone)