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Created with Raphaël 2.2.013Feb130Jan2824221014Dec1130Nov2920161087331Oct2919121117Sep13111010Aug763230Jul2719Jun829May2329Apr26Mar2523201916141398529Feb30Jan2314Dec1328Nov171331Oct111027Sep625Aug221816151084323Jun2May16Mar28Feb2720171410326Jan15Dec29Nov28231727Oct1713527Sep30Aug252416Jun26Apr22216130Mar6Jan18Nov1716121Oct12Aug7Jul315Apr25Feb24179Dec14Aug431Jul1730Jun10522May21201530Apr2517144128Mar20527Feb2614621Jan14920Dec1816429Nov2826221530Oct25241824Sep1893230Aug2822147529Jul24Jun22May211086330Apr262523151258Mar5128Feb2625211915141311528Jan14Dec22Nov16152Oct31Aug293110Jul9621Jun1925May242218148724Apr231817131254330Mar2815131276529Feb31Jan24174Nov2genrams: cleanup of inferred_async_fifosdlamprid-devdlamprid-devcrossbar: add possibility to silence info messages during simulationintroduce sfp i2c adapter modulehdl: minor cleanup of async fifos sourceshdl: implement g_show ahead for async fifoshdl: add label and fix sensitivity list for p_rd_ptr_mux process in inferred sync fifogc_sync_word_wr: improve speed (use toggling).proposed_masterproposed_mastergc_sync_ffs: add a comment.Add gc_sync_word_wr module.tools/sdb_desc_gen.tcl: try to figure out remote url when remote name is not "origin"xwb_axi4_bridge: conform (hopefully more) to the AXI4 specificationwrpc-v4.2-sis83…wrpc-v4.2-sis8300kuxwb_register: introduce FSM for proper handling WB classic ACKswishbone_pkg: remove unused declarations.sim: import onewire simulation model from opencores projectIntroduce new WB registerIntroduce new WB cross clocking bridgewb_slave_adapter: in the P2C scenario, only strobe ACK/ERR/RTY for 1 cycle.wb_reg_link: rename folder to wb_registerwb_crossbar: introfuce generic to control WB mode (classic, pipelined) for SDB ROM WB interfacexwb_clock_crossing: add some clarifications in commentsgenrams: fix typo in inferred async fifoswb_reg_link: add generics for instantiating wb adapters, since wb_reg_link works correctly only when used with pipelined wb interfaceswb_pkg: declare arrays for data64 wishbone recordsxwb_register_link: also register the CYC signal, otherwise STB remains active for one more cycle after CYC is dropped, which is not compliant with Wishbonehdl: introduce new reset core, based on asynchronous assert, synchronous deassertadd dual reset virtex6 native fifogc_ds182x_interface: fix constant declarationgenrams/xilinx: remove optimizations for ram initializationtom-sis83ktom-sis83kGeneralize f_reduce_or.wishbone: move register_link to its own directory.gc_multichannel_frequency_meter: fix architecture name error in synthesiswb_pkg: add types for wishbone interfaces with 64-bit datawb/xwb_register_link: drive unused output to zero to reduce warningscommon: added a simple non-WB SPI mastercommon: added a multiple input clock frequency meterintroduce gc_ds182x_readout and make gc_ds182x_interface wrap around itgc_ds182x_interface: code cleanupgc_ds182x_interface: added internal PPS generator[VXS] adding files to Manifests so that hdlmake can export everything neededWR-BTrain-VXSWR-BTrain-VXScommon: added a multiple input clock frequency metertom-sep16tom-sep16