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hdl-core-lib
ddr3-sp6-core
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master
bb5b8f75
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sim: auto-include ddr3 model when simulating
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Dec 13, 2018
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develop
004faf64
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Improve performance in the Wishbone interface
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Jul 12, 2015
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dev_theim
default
3b7baa89
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Deadlock fix, to be tested
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Jun 23, 2015
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vfc_bank1_64b_32b
5c639eab
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Modify top Manifest for vfc_bank1_64b_32b branch.
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Jul 19, 2013
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vfc_bank1_32b_32b
496d969a
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Modify top Manifest for vfc_bank1_32b_32b branch.
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Jul 19, 2013
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svec_bank4_64b_32b_bank5_64b_32b
dc197e6e
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Modify top Manifest for svec_bank4_64b_32b_bank5_64b_32b branch.
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Jul 19, 2013
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svec_bank4_32b_32b_bank5_32b_32b
270ad842
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Modify top Manifest for svec_bank4_32b_32b_bank5_32b_32b branch
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Jul 19, 2013
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spec_bank3_64b_32b
7496ea02
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Modify top Manifest for spec_bank3_64b_32b branch.
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Jul 19, 2013
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spec_bank3_32b_32b
c97c2623
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Modify top Manifest for spec_bank3_32b_32b branch.
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Jul 19, 2013
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