Merge requests · Projects

funtion timer_get_tics returns uint32_t

wrpc-sw!6 · created Mar 22, 2023 by Peter Jansweijer wrpc-v5
- Merged
- 1
updated Mar 22, 2023
remove Altium project from the repo, it's stored in EDMS now

diot-sb-igl!6 · created Mar 17, 2023 by Grzegorz Daniluk
- Merged
- 0
updated Mar 17, 2023
Develop merge master

hdl-make!25 · created Mar 13, 2023 by Tristan Gingold develop
- Merged
- 0
updated Mar 13, 2023
Merge master into develop

hdl-make!24 · created Mar 10, 2023 by Tom Levens develop
- Merged
- 1
updated Mar 13, 2023
Fixes for XCI parsing in Python 3.6

hdl-make!23 · created Mar 10, 2023 by Tom Levens
- Merged
- 0
updated Mar 11, 2023
Rework XCI file parsing

hdl-make!22 · created Mar 10, 2023 by Tom Levens
- Merged
- 4
updated Mar 11, 2023
Peter gain shed

wrpc-sw!5 · created Feb 23, 2023 by Peter Jansweijer wrpc-v5
- Closed
- 3
updated May 22, 2023
Merge proposed master into master

general-cores!29 · created Jan 16, 2023 by Dimitris Lampridis
- Merged
- 1
updated Jan 17, 2023
Adding Testbench for AXI cores

general-cores!28 · created Jan 13, 2023 by Konstantinos Blantos proposed_master
- Merged
- 18
updated Jan 16, 2023
WIP: Kostas dev

general-cores!27 · created Jan 13, 2023 by Konstantinos Blantos proposed_master
- Closed
- 0
updated Jan 13, 2023
Revert gtp_bitslide.vhd SHA-1: c9cc5cab4a1b0868391d32726c017816f4749a62 back to…

wr-cores!3 · created Jan 13, 2023 by Peter Jansweijer wrpc-v5
bug
- Closed
- 5
updated Dec 12, 2023
Avoid the generation of a latch during synthesis

wr-cores!2 · created Jan 13, 2023 by Peter Jansweijer wrpc-v5
- Merged
- 0
updated Jun 07, 2023
Add partial support for VHDL generic packages

hdl-make!21 · created Jan 12, 2023 by Augusto Fraga Giachero develop
feature
- Merged
- 1
updated Jan 13, 2023
2 new WB cores

general-cores!26 · created Dec 15, 2022 by Tomasz Wlostowski proposed_master
- Merged
- 4
updated Dec 16, 2022
Genrams improvements

general-cores!25 · created Dec 15, 2022 by Tomasz Wlostowski proposed_master
- Merged
- 2
updated Dec 16, 2022
DSP core collection

general-cores!24 · created Dec 15, 2022 by Tomasz Wlostowski proposed_master
- Closed
- 3
updated May 08, 2023
Minor updates to the AXI4 package

general-cores!23 · created Dec 15, 2022 by Tomasz Wlostowski proposed_master
- 3
updated Dec 16, 2022
Rework of SystemVerilog shared simulation code

general-cores!22 · created Dec 15, 2022 by Tomasz Wlostowski proposed_master
- 5
updated Dec 16, 2022
Resolve "tools: generate version information in gen_sourceid.py"

general-cores!21 · created Dec 15, 2022 by Dimitris Lampridis
- Merged
- 2
updated Dec 15, 2022
WIP: Relicense

vme-sbc-a25-pcie-vme-bridge!1 · created Nov 30, 2022 by Federico Vaga
- Merged
- 0
updated Dec 19, 2022