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connect heat-sink mounting hole to GND
diot-sb-zu#196
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Done
Minor
CLOSED
7
updated
Sep 08, 2020
[L1] what is the role of pads e.g. on WR_DAC lines (DIN, SYNC1, SYNC2, SCLK)?
diot-sb-zu#174
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Question
CLOSED
2
updated
Sep 04, 2020
"mouse bites" for PCB depanelization
diot-sb-zu#203
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Minor
CLOSED
5
updated
Sep 03, 2020
[General] Xilinx BGA package delays
diot-sb-zu#4
· opened
Jan 27, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
10
updated
Sep 03, 2020
[General] what is the estimated cost of this board today excluding the FPGA price?
diot-sb-zu#170
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Question
CLOSED
1
updated
Sep 03, 2020
add ground via under DDR chips
diot-sb-zu#204
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Done
Minor
CLOSED
1
updated
Sep 02, 2020
create xsignals between DDR chips for command signal group
diot-sb-zu#195
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Done
Major
CLOSED
2
updated
Sep 02, 2020
P1V8 power plane
diot-sb-zu#197
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Major
CLOSED
2
updated
Sep 01, 2020
[General] Impedance of differential pairs not always 100 Ohm, very thin traces (0.075mm)
diot-sb-zu#146
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
2
updated
Sep 01, 2020
various board texts
diot-sb-zu#214
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Done
Minor
CLOSED
1
updated
Aug 31, 2020
[L1] IC22, IC32 layout
3 of 3 tasks completed
diot-sb-zu#225
· opened
Jul 06, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
0
updated
Aug 31, 2020
[L1] Switching current loops for IC31/IC30 are not small
diot-sb-zu#224
· opened
Jul 06, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Minor
CLOSED
6
updated
Aug 31, 2020
larger antipads on gnd and power planes
diot-sb-zu#223
· opened
Jul 06, 2020
by
Grzegorz Daniluk
layout-v1.0
Minor
CLOSED
1
updated
Aug 31, 2020
some nets not connected to the centre of the VIA
15 of 15 tasks completed
diot-sb-zu#222
· opened
Jul 06, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Minor
CLOSED
0
updated
Aug 31, 2020
possible cross-talk between L7, L8?
diot-sb-zu#220
· opened
Jul 06, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Question
CLOSED
2
updated
Aug 31, 2020
spacing between ESD strip 1 and 2 should be 20mm
diot-sb-zu#219
· opened
Jul 06, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Minor
CLOSED
2
updated
Aug 31, 2020
check if SFP inserted in the cate will not conflict with the front panel extraction handle
diot-sb-zu#218
· opened
Jul 06, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
4
updated
Aug 31, 2020
[L14] X:199.75mm Y:25.825mm potentially unrouted net MGT2_RxC_P - consisting of 2 traces barely connected together
diot-sb-zu#217
· opened
Jul 06, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
1
updated
Aug 31, 2020
stitch board outline with gnd vias wherever possible
diot-sb-zu#216
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Done
Minor
CLOSED
0
updated
Aug 31, 2020
maximise decoupling capacitor track widths
diot-sb-zu#215
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Done
Minor
CLOSED
0
updated
Aug 31, 2020
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