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Not enough reference planes in the board stack-up
fmc-profinet#78
· opened
Mar 18, 2021
by
Christos Gentsos
layout-v1.0
critical
Layout Review V1.0
CLOSED
2
updated
May 17, 2021
PCB: URL and OHL text missing
fmc-profinet#51
· opened
Mar 16, 2021
by
Erik van der Bij
layout-v1.0
critical
Layout Review V1.0
CLOSED
2
updated
May 17, 2021
Frontpanel: shows XXXXX
fmc-profinet#50
· opened
Mar 16, 2021
by
Erik van der Bij
layout-v1.0
critical
Layout Review V1.0
CLOSED
2
updated
May 17, 2021
Provide clean return path by providing each GND pin with its own via to GND plane
fmc-profinet#69
· opened
Mar 18, 2021
by
Grzegorz Daniluk
layout-v1.0
critical
CLOSED
1
updated
May 16, 2021
Change test points to a different component with smaller footprint
fmc-profinet#80
· opened
Mar 19, 2021
by
Grzegorz Daniluk
layout-v1.0
cosmetics
CLOSED
0
updated
May 06, 2021
Unify traces thickness
fmc-profinet#79
· opened
Mar 19, 2021
by
Grzegorz Daniluk
layout-v1.0
cosmetics
CLOSED
0
updated
May 06, 2021
[L7] create void opening in the Chassis polygon
fmc-profinet#82
· opened
Mar 22, 2021
by
Grzegorz Daniluk
layout-v1.0
critical
CLOSED
0
updated
May 06, 2021
Missing magnetics for RJ45 connectors
fmc-profinet#66
· opened
Mar 17, 2021
by
Christos Gentsos
layout-v1.0
critical
Layout Review V1.0
CLOSED
2
updated
Apr 12, 2021
Analog power rails should be decoupled against AGND
fmc-profinet#65
· opened
Mar 17, 2021
by
Christos Gentsos
layout-v1.0
Layout Review V1.0
CLOSED
1
updated
Mar 30, 2021
external trigger
fmc-profinet#72
· opened
Mar 18, 2021
by
Paul PERONNARD
layout-v1.0
CLOSED
1
updated
Mar 25, 2021
Missing decoupling capacitors from ERTEC's (IC16) analog power supply pins
fmc-profinet#64
· opened
Mar 17, 2021
by
Christos Gentsos
layout-v1.0
Layout Review V1.0
CLOSED
2
updated
Mar 24, 2021
Flash.SchDoc both flash chips have the same enable signals and DQ0..15, this will not work
fmc-profinet#81
· opened
Mar 19, 2021
by
Grzegorz Daniluk
layout-v1.0
critical
CLOSED
1
updated
Mar 19, 2021
RJ45 connector wrong pinout
fmc-profinet#67
· opened
Mar 17, 2021
by
Christos Gentsos
layout-v1.0
critical
Layout Review V1.0
CLOSED
1
updated
Mar 19, 2021
[General] minor impedance discontinuities - on slow LVDS improve only if possible
diot-sb-zu#162
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Minor
CLOSED
1
updated
Sep 08, 2020
[L5] DDR4 PAR signal (FPGA pin AH18), minor plane crossing with L4PWR.
diot-sb-zu#163
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Minor
CLOSED
1
updated
Sep 08, 2020
[General] Clearance to unplated holes is a bit too tight
diot-sb-zu#149
· opened
Jul 01, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
1
updated
Sep 08, 2020
boot mode function table
diot-sb-zu#211
· opened
Jul 03, 2020
by
Paul PERONNARD
layout-v1.0
Done
Minor
CLOSED
3
updated
Sep 08, 2020
verify power polygons
3 of 3 tasks completed
diot-sb-zu#221
· opened
Jul 06, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Question
CLOSED
4
updated
Sep 08, 2020
[fpga-pl-mgts] SATA_TX vs SATAC_TX have P/N swapped!
diot-sb-zu#227
· opened
Aug 31, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
0
updated
Sep 08, 2020
[L14] X:124mm Y:30mm move SFP.MGT_Tx_P/N so that it lays fully over continuous GND in L13.
diot-sb-zu#228
· opened
Sep 04, 2020
by
Grzegorz Daniluk
layout-v1.0
Done
Major
CLOSED
0
updated
Sep 08, 2020
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