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[FPGA_Bank_66_67_68_DDR] forbidden I/O assignment
diot-pfc-ku#76
· opened
Jul 06, 2021
by
Grzegorz Daniluk
layout-v1.0
major
CLOSED
1
updated
Jul 07, 2021
Consider making core between L6 and L7 thicker
fmc-profinet#91
· opened
Jun 03, 2021
by
Christos Gentsos
layout-v1.0
Layout Review V1.0
CLOSED
1
updated
Jun 07, 2021
The P1V5 and VADJ planes stray unneccessarily
fmc-profinet#90
· opened
Jun 03, 2021
by
Christos Gentsos
layout-v1.0
Layout Review V1.0
CLOSED
4
updated
Jun 08, 2021
The P1V5 plane gets way too thin at certain points
fmc-profinet#89
· opened
May 10, 2021
by
Christos Gentsos
layout-v1.0
Layout Review V1.0
CLOSED
2
updated
Jun 03, 2021
The ERTEC IC is missing decoupling capacitors on its Vadj bank
fmc-profinet#88
· opened
May 07, 2021
by
Christos Gentsos
layout-v1.0
Layout Review V1.0
CLOSED
2
updated
Jun 03, 2021
L10: expand Vadj plane at X:4962mil Y:4289mil
fmc-profinet#87
· opened
May 06, 2021
by
Grzegorz Daniluk
layout-v1.0
CLOSED
1
updated
Jun 03, 2021
remove acid traps at some pads
fmc-profinet#86
· opened
May 06, 2021
by
Grzegorz Daniluk
layout-v1.0
cosmetics
CLOSED
1
updated
Oct 26, 2023
[L7] create void opening in the Chassis polygon
fmc-profinet#82
· opened
Mar 22, 2021
by
Grzegorz Daniluk
layout-v1.0
critical
CLOSED
0
updated
May 06, 2021
Flash.SchDoc both flash chips have the same enable signals and DQ0..15, this will not work
fmc-profinet#81
· opened
Mar 19, 2021
by
Grzegorz Daniluk
layout-v1.0
critical
CLOSED
1
updated
Mar 19, 2021
Change test points to a different component with smaller footprint
fmc-profinet#80
· opened
Mar 19, 2021
by
Grzegorz Daniluk
layout-v1.0
cosmetics
CLOSED
0
updated
May 06, 2021
Unify traces thickness
fmc-profinet#79
· opened
Mar 19, 2021
by
Grzegorz Daniluk
layout-v1.0
cosmetics
CLOSED
0
updated
May 06, 2021
Not enough reference planes in the board stack-up
fmc-profinet#78
· opened
Mar 18, 2021
by
Christos Gentsos
layout-v1.0
critical
Layout Review V1.0
CLOSED
2
updated
May 17, 2021
Routing for memories
fmc-profinet#77
· opened
Mar 18, 2021
by
Grzegorz Daniluk
layout-v1.0
question
CLOSED
2
updated
May 17, 2021
[L10] X:5200mil Y:3900mil P3V3A polygon stretch can be removed as it does not connect to anything
fmc-profinet#76
· opened
Mar 18, 2021
by
Grzegorz Daniluk
layout-v1.0
cosmetics
CLOSED
1
updated
May 17, 2021
[L1] X:4653mil Y:4085mil very thin 4mil track to P3V3 decoupling cap
fmc-profinet#75
· opened
Mar 18, 2021
by
Grzegorz Daniluk
layout-v1.0
CLOSED
1
updated
May 17, 2021
external trigger
fmc-profinet#72
· opened
Mar 18, 2021
by
Paul PERONNARD
layout-v1.0
CLOSED
1
updated
Mar 25, 2021
FMC connector: Use separate via for each power pin
fmc-profinet#71
· opened
Mar 18, 2021
by
Grzegorz Daniluk
layout-v1.0
critical
CLOSED
1
updated
May 17, 2021
Provide clean return path by providing each GND pin with its own via to GND plane
fmc-profinet#69
· opened
Mar 18, 2021
by
Grzegorz Daniluk
layout-v1.0
critical
CLOSED
1
updated
May 16, 2021
Remove GND polygons from signal layers
fmc-profinet#68
· opened
Mar 18, 2021
by
Grzegorz Daniluk
layout-v1.0
critical
CLOSED
1
updated
Jun 03, 2021
RJ45 connector wrong pinout
fmc-profinet#67
· opened
Mar 17, 2021
by
Christos Gentsos
layout-v1.0
critical
Layout Review V1.0
CLOSED
1
updated
Mar 19, 2021
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