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More GND stitching vias around criticial signal vias
wr2rf-vme#66
· opened
Oct 23, 2020
by
Tomasz Wlostowski
layout
for-DEM
important
CLOSED
1
updated
Oct 27, 2020
Increase distance between J1 and SFP
wr2rf-vme#64
· opened
Oct 20, 2020
by
Mattia Rizzi
layout
for-DEM
CLOSED
2
updated
Oct 21, 2020
Remove soldermask from ESD strip
wr2rf-vme#63
· opened
Oct 19, 2020
by
Tomasz Wlostowski
layout
for-DEM
CLOSED
1
updated
Oct 21, 2020
With just one pair of vias, connect the fast caps first, not the big ones
wr2rf-vme#62
· opened
Oct 19, 2020
by
Tomasz Wlostowski
layout
for-DEM
CLOSED
1
updated
Oct 21, 2020
Consider adding ground guard traces to the OCXO clock and the GTX lines
wr2rf-vme#61
· opened
Oct 19, 2020
by
Tomasz Wlostowski
layout
for-DEM
CLOSED
5
updated
Oct 23, 2020
Plane resonance at low frequencies (around 300MHz)
wr2rf-vme#59
· opened
Oct 19, 2020
by
Tomasz Wlostowski
layout
for-DEM
CLOSED
2
updated
Oct 21, 2020
Net NetC304_2 (for IC86's feedback) passes right over LVDS signals
wr2rf-vme#57
· opened
Oct 19, 2020
by
Tomasz Wlostowski
layout
for-DEM
CLOSED
2
updated
Oct 21, 2020
Fix FPGA pin assignment
wr2rf-vme#55
· opened
Oct 19, 2020
by
Tomasz Wlostowski
layout
for-DEM
CLOSED
2
updated
Oct 21, 2020
DRC rules incomplete for vias under pads.
wr2rf-vme#53
· opened
Oct 19, 2020
by
Tomasz Wlostowski
layout
for-DEM
CLOSED
1
updated
Oct 21, 2020
trigger regulators
wr2rf-vme#48
· opened
Oct 16, 2020
by
Mattia Rizzi
layout
critical
CLOSED
1
updated
Oct 19, 2020
P1V0 plane
wr2rf-vme#47
· opened
Oct 16, 2020
by
Mattia Rizzi
layout
critical
CLOSED
1
updated
Oct 19, 2020
Delay matching of RF_CH2.MAIN.IQDAC data lines
wr2rf-vme#46
· opened
Oct 15, 2020
by
Mattia Rizzi
layout
for-DEM
important
CLOSED
3
updated
Oct 23, 2020