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FPGA Bank Assignment
svec7#12
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
0
updated
Feb 19, 2020
GTX Transcivers mapping
svec7#11
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
1
updated
Feb 12, 2020
FMC Connectors
svec7#10
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
0
updated
Feb 19, 2020
Power supply
3 of 3 tasks completed
svec7#9
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
7
updated
Mar 23, 2020
Slow I/O
svec7#8
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
3
updated
Feb 19, 2020
Flash memory
svec7#6
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
1
updated
Mar 01, 2020
Change the DDR memory to a DDR SO-DIMM module socket (no ECC)
svec7#5
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
3
updated
Feb 19, 2020
Remove the discrete DDR chips (IC28, IC4)
svec7#4
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
1
updated
Feb 10, 2020
Remove J1 and J16 (stand-alone power port)
svec7#3
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
3
updated
Jul 02, 2020
Change the FPGA to XC7K160T-2FBG676
svec7#1
· opened
Feb 05, 2020
by
Mikolaj Sowinski
Ready for schematic review (CTI internal)
design
CLOSED
1
updated
Feb 25, 2020